6502.org

10 6502 Cores are compared as far as the resources consumed in an XC2S200. No speed or performance comparisons are made here, that may be for another thread!

The Spartan 2 family was chosen for their 5v input compatibility.
Xilinx ISE 10.1 is used although very "buggy" (read:not impossible to work with), because all future versions of ISE are exclusive of the Spartan 2 family.

I chose the XC2S200 208-pin QFP after trying a smaller XC2S100, which did not have enough resources to fit any of the cores presented here.

For each Core, there are pics of:
1. The pin assignments of the symbol, representative of each authors' HDL creation.
2. ISE10.1 Summary of each of the cores after passing ISE synthesis.

Most cores are still works in progress. Check out their links!
I will try to keep them up to date.

Here are the Cores in no particular order:

1) The T65 Core, by Daniel Wallner & Mike J. , maintained @ opencores.org :

http://i207.photobucket.com/albums/bb73 ... ematic.jpg

http://i207.photobucket.com/albums/bb73 ... ummary.jpg

2) The MyCpu core, by Dennis Kuschel:

http://i207.photobucket.com/albums/bb73 ... ematic.jpg

http://i207.photobucket.com/albums/bb73 ... ummary.jpg

3) Peter Wendrich's cycle exact 6502/6510 Core:

http://i207.photobucket.com/albums/bb73 ... ematic.jpg

http://i207.photobucket.com/albums/bb73 ... ummary.jpg

4) Retromaster's Core:

http://i207.photobucket.com/albums/bb73 ... ematic.jpg

http://i207.photobucket.com/albums/bb73 ... ummary.jpg

5) RUUD's rb65-10d Core. DDR Phase 2?:

http://i207.photobucket.com/albums/bb73 ... ematic.jpg

http://i207.photobucket.com/albums/bb73 ... ummary.jpg

6) Rob Finch's 6502 Core:

http://i207.photobucket.com/albums/bb73 ... ematic.jpg

http://i207.photobucket.com/albums/bb73 ... ummary.jpg

7) Sprow's 6502 Core:

http://i207.photobucket.com/albums/bb73 ... ematic.jpg

http://i207.photobucket.com/albums/bb73 ... ummary.jpg

8) A Rockwell R6502 true cycle Core, by Jens Gutschmidt, maintained @ opencores.org:

http://i207.photobucket.com/albums/bb73 ... ematic.jpg

http://i207.photobucket.com/albums/bb73 ... ummary.jpg

9) A Rockwell R65C02 true cycle Core, by Jens Gutschmidt, maintained @ opencores.org:

http://i207.photobucket.com/albums/bb73 ... ematic.jpg

http://i207.photobucket.com/albums/bb73 ... ummary.jpg

10) Arlet Ottens' 6502 Core:

http://i207.photobucket.com/albums/bb73 ... ematic.jpg

http://i207.photobucket.com/albums/bb73 ... ummary.jpg

I'll be happy to update this comparison if anyone knows of another 6502 core.
Many thanks to these creators who have made their software available to fellow enthusiasts.
(Edit #1 ):added Retromaster & RUUD on 10-26-10 by request of BigEd.
(Edit #2 ):added Rob Finch on 10-26-10 by request of BigEd.
(Edit #3 ):Re-clarified title....
(Edit #4 ):added Sprow on 10-26-10 by request of BigEd.
(Edit #5 ):added Arlet Ottens on 10-27-10 by request of BigEd.
(Edit #6 ):added Jens Gutschmidt's on 10-27-10 by request of BigEd.
(Edit #7 ):found problems with my update to #8 - Rockwell R65C02. deleted results...Added table.
(Edit #8 ):Re-added R6502 & R65C02. Updated table
(Edit #9 ): Fixed mispost on Arlen Ottens' Core. Updated Table
(Edit #10 ): Replaced my table with BigEd's.
(Edit #11 ): Fixed Peter Wendrich's link.
(Edit #12 ): Updated Rob Finch's link

Hi EE
nice idea - thanks for doing that and sharing!

please have a go with retromaster's core from his A2601 project.

(It might be intersesting to try Ruud's RB6502 as well, although we know it's not yet finished and not yet small.)

Cheers
Ed

RUUD's and Retromaster's added.

Glad to help as much as I can....

I'm not advanced enough to create a core, but I can evaluate different cores at this point. I hope these guys won't object to my idea of sharing their creations. Although if they do, just PM me. I fully understand. Hard work is not easily shared, and I will edit accordingly.

Hi EE
there's also Rob Finch's bc6502 core (verilog, but shouldn't be an issue)

By the way, I'm thinking a table would be good. (Edit: table now patched into the headline post, so I'll remove my copy to reduce possible confusion)

Cheers
Ed

Edit: updated the table, from EE's screenshots.
Edit: fix typo
Edit: removed table as EE now includes it

Hi EE
a few more 6502 cores (various licenses):

• Jens Gutschmidt's cpu6502_true_cycle
  Arlet Ottens' core http://ladybug.xs4all.nl/arlet/fpga/6502/ (often offline)
  Sprow's enhanced Free6502 (and also there, the original version 0.7 from free-ip, without decimal mode)
  Prof. Naohiko Shimizu's m65 core GPL, verilog, derived from higher-level description

I apologize for not checking the latter requests' licenses, but since I am not posting code, just a link back to their own site, I hope there won't be a problem...

I'll have to look over this tomorrow: "Prof. Naohiko Shimizu's m65 core GPL, verilog, derived from higher-level description"...

thanks for the new results - I've updated the table. The sprow and true cycle look very similar - I haven't compared the code.

Let me re-check those 2 entries...

I was rushing. Sprow's is correct.

Arlet Ottens done. He makes you work for it!

Jens Gutschmidt's is done. I decided to go with his R65C02 core instead. Very well documented.

Trying the professor's... I get a license expired when I try his sfl2vl converter.

Hi EE
thanks for the updates. I thought I knew of a couple more cores, but they are already in your collection.

There is one more, but it's in System Verilog and I don't know if that will be digestible. See hmc-6502 project - I think it may be incomplete, but might be interesting for someone to study (or finish!) I've noted elsewhere that this core comes with a testsuite which might be useful for other projects.

Sorry about the sfl core - I'd got the impression that the verilog version was included in the package, but in fact it's only the high-level description, and the Altera gate level result. It's an interesting example: he says it only took him a week to design and it's nearly cycle accurate. I'm a firm believer in higher-level languages allowing higher productivity, but that's very impressive. I'll see if I can dig up or produce the verilog somehow.

I've updated my table with your latest results. It might be interesting to put Jen's other core back into the collection, unless you've checked and it's just a version of the Free6502 (like sprow's is) - the 6502_tc seems a lot smaller than the 65c02_tc

Cheers
Ed

Edit: looking at m65 (subsetted) implementation files, I see 96 flops and 455 LUTs.

Lots of these 6502 Cores are incomplete.... I'll see if I can get some results on the hmc-6502 project. I'll add your table after this last possible addition...

I'll definately post Jens original R6502. His documentation on all his work was painstakingly done. Attention to detail is always key to success...

Edit: I took off my results from Jens R65C02 Core. Repeatability was not there. I must have got lucky earlier.... It does involve adding a new vhdl library which I am not fully experienced at. Plus, there is alot of info! 32MB worth to look over. I'll get it straight. Might take a couple days though... It would be a disservice to post erroneous information.

Turns out there's another bug I came across, this one when adding a library...

Hallo Ed,
Thank for the table! Now I have something to compare my core with. I knew I used almost twice as much resources as T65 but I'm happy I'm not the biggest :)

But a question from a newbie: what are flops, slices and LUTs? And what should I change to my design to decrease them? TIA!

Hi Ruud
there's an accessible story about slices and so on here.

(Basically, an FPGA of a given size has some number of slices, which are all the same, and probably some RAM blocks and multipliers. In the FPGAs we're talking about, a slice has 2 bits of storage (flops), 2 muxes and 2 general 4-input logic units. These logic units are called LUTs because they are actually look-up tables. In fact you can use them for storage although they are not as dense as the RAMs)

To an approximation, all that matters is whether your design fits on your FGPA or not. But if your core needs to share the FPGA with some interesting other system logic, the fewer slices it uses the more room will be left.

There's probably a weak correlation that bigger designs would be slower, unless very carefully arranged otherwise.

I find it interesting that the different designs have such different numbers of flops (storage elements) because they are all implementing 6502 with the known number of programmer visible registers. The differences must come from the internal (hidden) registers they have, and the amount of control state. For example, if you had registered every output of a PLA-like module, that would be 132 extra flops. (The real 6502 doesn't do that)

Hope this helps
Ed

Another criteria is whether or not they're synthesizing directly off of a behavioral model, or they're reducing their design to register-transfer logic, or if they're going further down to gate level design. I suspect, with each layer of manual optimization, you can get progressively tighter layouts.

ISE has a Design Goals and Strategy Editor that lets you modify alot of variables. I've not gone beyond the default settings in ISE 10.1 though. It would be an interesting experiment to tweak the Editor for higher speeds once a Core is chosen/implemented and wired up... I'm not quite there yet. Soon though, very soon.

Speaking of 6502 cores, looking @ the T65 project leads me to believe they've abandoned the 6502 and are starting on the 65816. One unfortunate thing about opencores.org, is that there seems to be no history from earlier progress on the T65. Everyone has always talked about the latest, heh. Now it's too late for a T65 6502 core?

Oooh, nice! I'm excited by the possibility of an open-source 65816 clone. I wonder if it can be driven to 33MHz or faster? Or, how easy it'd be to hack it into a genuine 16-bit (or even 24-bit) processor internally? Think of how neat it'd be (and, for that matter USEFUL) to have a 33MHz 65816 that can grok PCI natively.