6502.org

Posted: **Fri Sep 12, 2025 5:45 am**

Also... the datasheet does not explicitly state so, but you should be able to use a oscillator module directly to the clock input pin(s), leaving the output pin (an inversion of the input, according to the datasheet) unconnected. That may reduce your concerns about the crystal circuits (though they will work!)

Neil

Posted: **Sat Sep 13, 2025 2:40 am**

It was slow going but I managed to do the following:

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Changed the mounting holes to 3.2mm which should allow either M3 or 4-40 bolts.
Double checked XBUS, J4, J5, J6, and VIA headers to make sure they're aligned with each other.
Moved some resistors to the front side of the board to allow routing traces under the w65c265.
Routed all bottom jack traces.
Changed EEPROM footprint to the low-profile ZIP socket.
Move components and traces to make space for the ZIF socket. It has about a 1/2 mm clearance between it the RAM socket.
Changed the width of the power traces to 0.4mm. That should be enough as this is only five CMOS ICs.

I think I'm getting close. Unless I want to try and migrate all components to the front side.

Posted: **Sat Sep 13, 2025 6:49 am**

Just two thoughts. I prefer to have all my surface mount components on the front side (as you've mentioned) because then I can hot-plate solder them in a single go. Very often I can't and then that's just a bit of time with a soldering iron.

I would suggest moving the power lines slightly in from the edge of the board in case the router is misaligned during manufacture

which happened on the board above. The mouse-bites are correctly placed* but the router is off my more than 0.5mm on some edges.

<edit>* I should have said correctly drilled rather than correctly placed. The router should have run straight towards the centre of the mouse bites.

Posted: **Sat Sep 13, 2025 3:29 pm**

AndrewP wrote:

Just two thoughts. I prefer to have all my surface mount components on the front side (as you've mentioned) because then I can hot-plate solder them in a single go. Very often I can't and then that's just a bit of time with a soldering iron.

I would suggest moving the power lines slightly in from the edge of the board in case the router is misaligned during manufacture.

Good points and thanks for the feedback.

I wondered if moving the SMD components to the front was worth it. Ideally the board would be useful to others, and they might use a hotplate for the SMD components. So, I will move them as it should be straightforward, except for C6 and C11 which are in in space constrained areas.

I had an inkling that putting the power rails right up to the edge might not be a good idea. But I was waiting until I was done with everything else before moving them in a mm or two.

Posted: **Sat Sep 13, 2025 5:14 pm**

I've never seen routing errors as gross as the 0.5mm mentioned above, even from the cheap board houses; but if the boards are panelized (rather that separate), you do have to be careful of the mousebites, unless the boards are just scored. Typically you just present the gerbers for one board, and the manufacturer decides how to panelize them and where to put the mousebites. (I think Dave Jones of EEVblog recommended sending the gerbers for an entire sub panel, including where to put the mousebites; but his CAD is a whole lot more expensive than mine.) I have had this kind of problem at work:

This is the bottom of an SMT board that's about the size of our common postage stamps in the US. It wasn't too big of a problem in this case; but you can see that if I had put a signal trace or chip capacitors that close to the edge on the other side, it would definitely be a problem.

Posted: **Sat Sep 13, 2025 7:16 pm**

I reworked the PCB so all SMD components are on the front side of the board. Hot plate users rejoice.
I pulled the power rails back from the edge of the board a bit, cut the corners, and increased their width to 1 mm.

KiCad made a change to the project file to change pad defaults from 2.7 mm to 1.6 mm, and drill size to 0.8mm. I didn't make that change, but I checked it in assuming KiCad knows what it's doing.

Attached is a picture of the latest revision. Tomorrow I will go over it with a fine-tooth comb looking for errors.

Posted: **Sat Sep 13, 2025 8:47 pm**

Looking good, Martin.

Neil

Posted: **Sun Sep 14, 2025 12:51 am**

@Neil, thanks!

@all, I have done the following QA steps.
* I spent time eyeballing the PCB and it looks good.

* I used the net inspection tool to validate the power and ground networks. All IC's get power and ground from the main power tracks with no loops inside the board. Nothing looked like it was missing power.

* I ran the design rules checker, and it found a number of small errors I corrected. However, the DS1813 footprint library has many problems, and I am not sure how to correct it.

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** Drc report for Mench Reloaded.kicad_pcb **
** Created on 2025-09-13T19:32:09-0400 **

** Found 22 DRC violations **
[lib_footprint_issues]: The current configuration does not include the footprint library 'ds1813_revised'.
    Local override; warning
    @(60.2500 mm, 84.2500 mm): Footprint IC1
[silk_over_copper]: Silkscreen clipped by solder mask
    Local override; error
    @(57.7100 mm, 84.2500 mm): PTH pad 1 [RESB] of IC1
[silk_over_copper]: Silkscreen clipped by solder mask
    Local override; error
    @(60.2500 mm, 84.2500 mm): PTH pad 2 [+5V] of IC1
[silk_over_copper]: Silkscreen clipped by solder mask
    Local override; error
    @(62.7900 mm, 84.2500 mm): PTH pad 3 [GND] of IC1
[silk_over_copper]: Silkscreen clipped by solder mask
    Local override; error
    @(58.8479 mm, 84.3770 mm): Segment of IC1 on F.Silkscreen
[silk_over_copper]: Silkscreen clipped by solder mask
    Local override; error
    @(61.3854 mm, 84.3770 mm): Segment of IC1 on F.Silkscreen
[silk_over_copper]: Silkscreen clipped by solder mask
    Local override; error
    @(62.9119 mm, 84.3770 mm): Segment of IC1 on F.Silkscreen
[silk_over_copper]: Silkscreen clipped by solder mask
    Local override; error
    @(60.2500 mm, 84.2500 mm): Arc of IC1 on F.Silkscreen
[silk_over_copper]: Silkscreen clipped by solder mask
    Local override; error
    @(60.2500 mm, 84.2500 mm): Arc of IC1 on F.Silkscreen
[silk_over_copper]: Silkscreen clipped by solder mask
    Local override; error
    @(60.2500 mm, 84.2500 mm): Arc of IC1 on F.Silkscreen
[silk_over_copper]: Silkscreen clipped by solder mask
    Local override; error
    @(60.2500 mm, 84.2500 mm): Arc of IC1 on F.Silkscreen
[silk_over_copper]: Silkscreen clipped by solder mask
    Local override; error
    @(60.2500 mm, 84.2500 mm): Arc of IC1 on F.Silkscreen
[silk_overlap]: Silkscreen overlap
    Rule: board setup constraints silk; error
    @(57.7100 mm, 84.2500 mm): PTH pad 1 [RESB] of IC1
    @(58.8479 mm, 84.3770 mm): Segment of IC1 on F.Silkscreen
[silk_overlap]: Silkscreen overlap
    Rule: board setup constraints silk; error
    @(57.7100 mm, 84.2500 mm): PTH pad 1 [RESB] of IC1
    @(60.2500 mm, 84.2500 mm): Arc of IC1 on F.Silkscreen
[silk_overlap]: Silkscreen overlap
    Rule: board setup constraints silk; error
    @(57.7100 mm, 84.2500 mm): PTH pad 1 [RESB] of IC1
    @(60.2500 mm, 84.2500 mm): Arc of IC1 on F.Silkscreen
[silk_overlap]: Silkscreen overlap
    Rule: board setup constraints silk; error
    @(57.7100 mm, 84.2500 mm): PTH pad 1 [RESB] of IC1
    @(60.2500 mm, 84.2500 mm): Arc of IC1 on F.Silkscreen
[silk_overlap]: Silkscreen overlap
    Rule: board setup constraints silk; error
    @(60.2500 mm, 84.2500 mm): PTH pad 2 [+5V] of IC1
    @(61.3854 mm, 84.3770 mm): Segment of IC1 on F.Silkscreen
[silk_overlap]: Silkscreen overlap
    Rule: board setup constraints silk; error
    @(62.9119 mm, 84.3770 mm): Segment of IC1 on F.Silkscreen
    @(62.7900 mm, 84.2500 mm): PTH pad 3 [GND] of IC1
[silk_overlap]: Silkscreen overlap
    Rule: board setup constraints silk; error
    @(60.2500 mm, 84.2500 mm): Arc of IC1 on F.Silkscreen
    @(62.7900 mm, 84.2500 mm): PTH pad 3 [GND] of IC1
[silk_overlap]: Silkscreen overlap
    Rule: board setup constraints silk; error
    @(62.7900 mm, 84.2500 mm): PTH pad 3 [GND] of IC1
    @(60.2500 mm, 84.2500 mm): Arc of IC1 on F.Silkscreen
[silk_overlap]: Silkscreen overlap
    Rule: board setup constraints silk; error
    @(62.7900 mm, 84.2500 mm): PTH pad 3 [GND] of IC1
    @(60.2500 mm, 84.2500 mm): Arc of IC1 on F.Silkscreen
[nonmirrored_text_on_back_layer]: Non-Mirrored text on back layer
    Local override; warning
    @(60.5000 mm, 86.9170 mm): Value field of IC1 (DS1813)

* I ran the Electrical Rules Checker" as gilhad recommended. Most of the output was weird warnings that I am unsure about. Here's a sample:

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ERC report (2025-09-13T20:03:50-0400, Encoding UTF8)

***** Sheet /
[footprint_link_issues]: The current configuration does not include the footprint library 'ds1813_revised'.
    ; warning
    @(750 mils, 1050 mils): Symbol IC1 [DS1813]
[lib_symbol_issues]: The current configuration does not include the symbol library 'oshec_ds1813_revised'
    ; warning
    @(750 mils, 1050 mils): Symbol IC1 [DS1813]
[lib_symbol_mismatch]: Symbol '+5V' doesn't match copy in library 'power'
    ; warning
[lib_symbol_mismatch]: Symbol 'LED_Small' doesn't match copy in library 'Device'
    ; warning
    @(3900 mils, 900 mils): Symbol D4 [L`ED_Small]

More concerning were the errors:

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***** Sheet /RAM, EEPROM, and headers/
[power_pin_not_driven]: Input Power pin not driven by any Output Power pins
    ; error
    @(7200 mils, 5400 mils): Symbol U4 Pin 3 [VI, Power input, Line]
[power_pin_not_driven]: Input Power pin not driven by any Output Power pins
    ; error
    @(9100 mils, 2650 mils): Symbol #PWR031 Pin 1 [Power input, Line]

Apparently, I need to assign PWR_FLAGs to the schematic, but I haven't found where I need to do this.

Another error was related to the quad Nand gate.

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[pin_not_connected]: Pin not connected
    ; error
    @(9800 mils, 2650 mils): Symbol U5 Pin 11 [Output, Inverted]

I had one unused gate, so I tied the inputs to ground to avoid floating inputs and left the output unconnected. But apparently the rules checker doesn't like this. I then found the unconnected option in the toolbad and that seems to have fixed it

Posted: **Sun Sep 14, 2025 1:48 am**

Martin_H wrote:

I reworked the PCB so all SMD components are on the front side of the board...I pulled the power rails back from the edge of the board a bit, cut the corners, and increased their width to 1 mm.

I’d be doing it in four layers and not sweating power or ground traces being too close to the PCB perimeter, or traces getting in the way of optimum routing. Why are you making it difficult for yourself?

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KiCad made a change to the project file to change pad defaults from 2.7 mm to 1.6 mm, and drill size to 0.8mm.

Something I don’t like is a CAD program making assumptions for me. It’s as annoying as a search engine posing a “Did you mean...?” prompt when I enter something that is a bit off the wall.

Posted: **Sun Sep 14, 2025 6:10 am**

Why use four layers if it can be done in two? We're not discussing a cost or performance optimised design here, or indeed in most of the projects discussed here. In many cases it's a matter of personal preference, and Martin's already stated he's new to this game. Which is not to say that there aren't good reasons for four (or more) layers but on the 4MHz circuit discussed here, I'd not worry about them.

@Martin:
Power flags define a particular network and to be honest I don't know exactly why (beyond the obvious setting of trace width) but it's easy to handle: you'll find them in the Power Symbols (use the button "Add Power Symbols"). Connect one to each circuit wide power and ground (usually Vcc and Gnd) - you don't need one, for example, for an unregulated power input between the fixed power plug and the regulator.

As you've discovered: Kicad tries to enforce a no unconnected pins requirement; this ensures that you have no inputs floating, and that any unused outputs are intentional. As you've discovered, the 'Place No Connect Flag' button provides a way to mark those on your schematic. (In general, Kicad is good at making sure inputs are connected to outputs and so on, by pin type from the original symbol definition. Sometimes you'll disagree and get a warning or error, but like a compiler, it's worth listening - also like a compiler, I tend to correct only the first error and then run the check again; often errors are caused by an earlier error and will go away when that's fixed).

Neil

Posted: **Sun Sep 14, 2025 7:20 am**

I think the idea is to attach PWRFLAGs to the thing that is supplying the power as that's not obvious to kicad - e.g. a barrel jack might be input or output. So apply one to VCC and one to GND in the schematic near your power source pins.

You can change some errors to warnings if you don't generally care about them, like the silkscreen ones, then it's easier to focus on electrical errors.

Posted: **Sun Sep 14, 2025 8:33 am**

barnacle wrote:

Why use four layers if it can be done in two? We're not discussing a cost or performance optimised design here, or indeed in most of the projects discussed here. In many cases it's a matter of personal preference, and Martin's already stated he's new to this game. Which is not to say that there aren't good reasons for four (or more) layers but on the 4MHz circuit discussed here, I'd not worry about them.

Aside from the ability of a four-layer design to pack more into a given space, such a board will exhibit a lot less ground-bounce and VCC sagging. In addition to those potential problems, WDC processors, especially the ones with TSMC 0.6µ dice, produce extremely rapid switching speeds whose deleterious effects have little to do with the Ø2 rate being used. Four-layer boards with inner ground and power planes help a lot in taming the ringing and noise caused by single-digit-nanosecond signal transitions.

Posted: **Sun Sep 14, 2025 10:08 am**

Martin_H wrote:

found a number of small errors

silkscreen is the yellow text, which is used to display values of resistors on the PCB, place, where parts should be placed etc. etc. anything about it is just cosmetical and can be safely ignored

[silk_over_copper]: Silkscreen clipped by solder mask
Some silkscreen is clipped by place around soldering pads to keep them clean and solderable, so it will look "ugly" = part of some text will be missed, unreadable, untidy - you may fix it by placing the text somewhere else, modify the text, or ignore it - it is just looks

[silk_overlap]: Silkscreen overlap - two or more silkscreen overlaps like crossing lines and text, both will be printed one over the other. No problem, but ugly

[nonmirrored_text_on_back_layer]: Non-Mirrored text on back layer - the text is placed back, and so it should be mirrored to be readable and to backwards. In the PCB editor you see the texts on the back side through the PCB. If you use the Atl+3 3D viewer you can rotate the PCB to see it how it will look and when you look on the bottom side, this text would be backwards there. Which you usually do not want.

* I ran the Electrical Rules Checker" as gilhad recommended. Most of the output was weird warnings that I am unsure about. Here's a sample:

[lib_symbol_mismatch]: Symbol 'XYZxyz' doesn't match copy in library 'SOMELIB'
you changed the library and did not update this symbol or copied symbol from other project or something like that. Your actual symbol is used, but you may want to synchronise everything (well or not want)

[power_pin_not_driven]: Input Power pin not driven by any Output Power pins - use PWR_FLAG to mark something as powersource, you know, where your power cam from, KiCad just try to make sure, that you did not forget power anything - place the flag anywhere on +5V and anywhere on GND nets.

[pin_not_connected]: Pin not connected
I had one unused gate, so I tied the inputs to ground to avoid floating inputs and left the output unconnected. But apparently the rules checker doesn't like this. I then found the unconnected option in the toolbad and that seems to have fixed it

Yes, it makes sure, that you connected all you wanted to connect and marked unconnected thing explicitely as unconected.

------

Anyway all these checks are there for you to be informed, what KiCad "things" about it. You may ignore them and the PCB will be then made as you draw it.
These errors and warnings are there so you notice, that maybe there is something what "computer will do exactly as you told it, not as you intended it"

Posted: **Sun Sep 14, 2025 2:06 pm**

@all, thanks for your feedback.

I updated the schematic, and this silenced all but six warnings in the ERC. The remainder were about the symbol library not containing the DS1813, the w65c265, and the RAM I am using. These don't appear to be critical, so I am ignoring them.

I updated the PCB from the schematic, and it only resulted in changes to description fields. I reran the DRC and 20 errors remained, and were all related to the DS1813 silkscreen errors mentioned previously. I believe it's because I downloaded a footprint for the DS1813 and the creator ignored these errors. As this is cosmetic and I don't want to create a custom footprint for this component, I will ignore it.

On to the next step. Where and how and where do I get this fabricated?

Posted: **Sun Sep 14, 2025 2:40 pm**

I use JLCPCB in China - cost is two bucks for five PCBs, plus postage and any import charges.

PCBWAY is one I haven't used but have heard good things of; five bucks but probably cheaper postage; I think they're a US based company.

Aisler are in Germany - so in some ways easier for me - but a little more expensive; I may be moving to them since Europe changed its rules in small imports from China.

I think all of those also offer build options, but how that works with components that aren't in their inventory - like the processor - I don't know. If you're planning on building it at home, you might want to get a stencil for the solder paste, but it's not strictly necessary: for the processor, I'd use a single thin stripe of solder paste down each side, put the chip on top, and stick it in an oven, on a hotplate, or use a hot-air gun. The rest, soldering iron with a suitable tip. You will find leaded solder _much_ easier than lead free.

Neil

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