Managing the 65816 multiplexed bus

[Dr Jefyll]

drogon wrote:

if you are thinking of making a 65816 system, then just do it - don't overthink it, just enjoy the process!

You make a good point, Gordon. I started this thread for a thorough and rather fussy investigation re: multiplexing and bus contention. But I didn't give any sense of scale regarding the importance or unimportance of the issue. It's worth pointing out that many have succeeded and been satisfied with the '816 despite being much less fussy than I.

That said, now is a good time to take a moment and explain why I care about the fine points.

Frankly, there's a degree of pride involved, because I admire designs that have beauty. And bus contention reminds me of an engine that knocks, shakes, and rattles during operation! Below a certain threshold, the ugliness of bus contention does become tolerable, but that threshold will vary depending on one's goals. And I want to improve my skills to the point where even very demanding goals become possible.

For example, battery operation means maximum efficiency will become a goal. Bus contention wastes battery energy. It also increases RFI emissions, which in some contexts may be important. But these are niche concerns. The goal that all of us can appreciate is speed, and a quiet machine is a fast machine! Bus contention aggravates ringing because it blasts pulses of energy into the inductance of the PCB traces, and if you don't avoid or at least minimize contention then you're obliged to adopt other measures to reduce ringing.

Chromatix wrote:

Also worth remembering the inherent characteristic of CMOS, which is that both transistors in the totem pole are briefly switched on simultaneously during their input's transition. [...] I would suggest that any temporary contention during bus turnaround is indistinguishable from the inherent shoot-through of the driving circuits.

Interesting point. I agree the two are analogous, but "indistinguishable" isn't the word I would choose. Yes, for modern CMOS the shoot-through period is extremely brief, but it's comparatively easy to approach perfection in respect to the behavior of one totem pole whose upper and lower halves were designed by the same engineer. Connecting two disparate chips is a whole other story. Also there's the added factor of the inductance in the connection between the two chips, as already noted.

BigEd wrote:

It's a recurring theme that WDC's offering, especially their documentation, falls short of best practice.

It's even possible that there's no bus contention, if the various underspecified and misdocumented parameters work out the right way.

Yes, I agree it's possible the parameters could work out in your favor. It's just that you have no advance assurance of that from WDC's datasheet. Speaking of which, just as a sanity check I decided to have a peek at datasheets for some other multiplexed-bus CPU's. 8086, 8088 and 8085(?) come to mind; I'm sure there are others. So far I only checked one. 80C86 was the datasheet I happened to find first online, and (unlike WDC's 816 datasheet) it DOES supply the figures I insist should be present.

apoloval wrote:

I make mistakes expressing myself, and I am too hasty. [...] Being isolated by COVID with 2-yo kids makes you optimise your time to the maximum.

Yoiks! We will definitely cut you some slack, then!

Speaking of hasty, I regret that my terse comment upthread prompted BDD to remove the timing diagram he posted. I will link to that diagram now. If I'm not mistaken it's the same one that's posted here.

Thanks to all for your responses,

Jeff