An Improved MENSCH™ Microcomputer

[Martin_H]

@Garth, thanks for the links, I will read them.

@George and Gordon, I like the jumper idea.

@gilhad, thanks for the validation pointers. I will use them.

@Neil, your layout and traces are elegant and attractive. Moving U5 and rearraigning the oscillator components paid dividends. I printed it out to ease study and learning from it. Also, I am trying to maintain more clearance around the EEPROM, as I will use a low profile Zif socket from Aries Electronics. They're expensive, but only slightly larger than a regular IC socket (41.9mm x 19.05mm), and worth it. I tried making a footprint for it, but haven't quite got it right yet.

@Bill, I strongly agree, and normally I build point to point on perf board where that is automatic. Does KiCad have a snap to grid option? The Arduino and its misaligned headers are a pain when trying to prototype.

@All, my big concern is that I am designing using the WDC schematics for the Mench, W65c265sxb, and W65c265QBX. The kernel of them is the same, and I understand what I reverse engineered. Normally I build and test circuits incrementally on perf or bread board, so upfront design without testing is new. The oscillators especially concern me as I know how twitchy they can be.

[gilhad]

Martin_H wrote:

Does KiCad have a snap to grid option? The Arduino and its misaligned headers are a pain when trying to prototype.

Preferences / PCB Editor / Display Options / Grid dissplay / Snap to Grid

Also you can change grid while editing so if you go from 0.1" to 0.05" for moment and back then, the Arduino "it wrong, but makes it more human" feature can be solved.
And snaping for routing uses more sources for alingment, so it can somehow work evne with missaligned parts

[barnacle]

It is important when aligning to a grid to select the correct part of the component footprint to me moved... all components have a centrum - a purple cross - which is what will try to align if you just click within the component; that is often, particularly with surface mount parts, not related particularly to the grid on which the feet live.

Select a convenient pin - corners are good - and then use the M move key. That pin will then align to your grid; the rest of the pins also (assuming your components and grid are related) will be on the grid.

With a square component like LQFP with pins on four sides, I've often rotated it 45 degrees, which allows me to run all the connections in one direction, either up-down or left-right without having to go through the middle of the chip. It can give a bigger layout, though, so it's not a panacea for all ills, and of course on that rectangular chip it wouldn't be very pretty!

You should be able to move the eeprom south perhaps 0.2", using up the space above the processor, without any serious issues. Though you might want to consider the power: as I've drawn it, basically the ground goes one way around the edge of the board and the power goes the other... it's a bit confusing as I copied it from your layout and didn't alter it much. I might consider completing the circle and making a power ring and a ground ring.

Neil

[gilhad]

I am little confused here - avoid ground loops - make ground ring - sounds contradictional for me - is here some simple explanation or some link/reference to discussion about it?

[Martin_H]

I checked in and pushed the following updates:

Code: Select all

* Added a +5V power selector header (FTDI vs battery and support traces).
* Added 128kB vs 256kB RAM selector, net classes and traces.
* Added a 3K pull up for RESB and DS1813.
* Reworked traces at top of the board using streets and avenues for the XBUS and RAM.

To do:

Code: Select all

* Rework oscillator components using Neil's layout.
* Finish footprint for low profile Zif socket to maintain space allowances when moving EEPROM North.
* Make sure XBUS, J4, J5, J6, VIA Port A, and VIA Port B headers are aligned on a 2.54mm grid.
* Move U5 into the location from Neil's layout.
* Rework traces from CPU into streets and avenues.
* Perform KiCad validation test.

@gilhad, I am likewise confused. I always heard ground loops were a recipe for weirdness.

[plasmo]

Ground ring and power ring are good things. My standard practice for 2-layer board is reducing the board size by 50mil for auto router, then using the 50mil space to manually add a thick ground ring at bottom and power ring at the top side. They provide additional return paths for the signals. This additional return paths are important for fast logic, it is not unusual for a strategically placed ground wire to fix noise problems in fast logic board.
Bill

[barnacle]

• https://www.allpcb.com/allelectrohub/analog-pcb-grounding-the-star-ground-myth-debunked
• https://resources.altium.com/p/using-pcb-star-grounding-can-keep-your-design-shining
• https://resources.pcb.cadence.com/blog/2020-what-is-a-star-ground-layout-and-why-do-you-need-it

These are comments from people who ought to know about this kind of thing, but the third rather disagrees with the first two.

The critical thing is low impedance return and supply paths. Because I worked for ten years in commercial product design which had to meet international EFI noise standards, I tended to use four layer boards with ground planes. For hobby stuff, I tend to go for a power plane either side, though that can have capacitative effects if it floods between conductors. But as Bill notes, a ground and power ring around the board is a good approximation.

I do think that on my layout for your design I should pay more attention to the power distribution; in particular the top right hand side should close the loop.

Neil

[BigDumbDinosaur]

gilhad wrote:

I am little confused here - avoid ground loops - make ground ring - sounds contradictional for me - is here some simple explanation or some link/reference to discussion about it?

Even more puzzling to me is why this project is not on a four-layer board with inner ground and power planes.  There’s relatively little cost difference these days between two- and four-layer PCBs from many board houses.  The upsides of using a four-layer board are several, not the least of which is the greater density that can be achieved with not having to dodge power and ground traces.

[gilhad]

On JLCpcb the difference for 10x10cm is 2$ vs 7$ (that is 3.5x higher).
Well it is just 5$ but still...
it is maybe more psychological, mainly when I consider, that I made my own PCBs at home, which was naturally 2 planes, so my mind is used to differenciate between DIY and commercial worlds.

[Martin_H]

BigDumbDinosaur wrote:

gilhad wrote:

I am little confused here - avoid ground loops - make ground ring - sounds contradictional for me - is here some simple explanation or some link/reference to discussion about it?

Even more puzzling to me is why this project is not on a four-layer board with inner ground and power planes.  There’s relatively little cost difference these days between two- and four-layer PCBs from many board houses.  The upsides of using a four-layer board are several, not the least of which is the greater density that can be achieved with not having to dodge power and ground traces.

You're correct and the problem is the PCB designer. He's struggling to learn KiCad, PCB design, and a two layer board. I don't know where we found this guy.

The good news is I was successful in creating a footprint for my low profile zif socket. The bad news is it took up too much board space to undo my rats nest traces. I will use a regular socket instead. That won't be a problem once I have an image I like, but during testing I could damage the EEPROM with insertion and removal. For testing I plan to put the zif socket into the board socket. That should raise the zif socket above the RAM to allow for temporary use. I can also make the EEPROM writeable, so it might be possible to update it on the board with a bootloader.

Changes since last update:
* Created a power and ground ring around the edge of the board.
* Moved EEPROM North to create more space for traces.
* Reworked all traces from CPU to fix rats nest wiring (whew).
* Added LED to csb2 to allow for debugging when internal bus is in use.
* Added more signal net classes to make data traces a consistent size.
* Git is up to date.

To do:
* Make sure the XBUS header and other headers are aligned to a grid before wiring the other connectors.
* Wire the other connectors.
* Validate the design using KiCad and the links Garth mentioned.

For the first bullet item. The XBUS pin 1 is at X 128, Y 49.5. That seems aligned to 0.1mm grid. I believe if I align the other headers so their pin 1 is a 2.54 mm multiple of that X and Y they'll be aligned as well?

[plasmo]

Just eye ball it, I’d say many of your connectors are not on 0.1” grid. They may be on 0.05” grid. Is your mounting holes on 0.1” grid?
Bill

[Martin_H]

plasmo wrote:

Just eye ball it, I’d say many of your connectors are not on 0.1” grid. They may be on 0.05” grid. Is your mounting holes on 0.1” grid?
Bill

Good point about the mounting holes. I started with a Eurocard template and shrunk it to 100mm square, so the hole location isn't well thought out. I moved all of them, so their centers are 10mm from each edge. Their footprint is MountingHole_2.7mm_M2.5_DIN965 which would fit a metric M2.5, but may be a smidge too small for a US 4-40 standoff. The next size up is 3mm which may be a better choice.

I am most concerned with the position of the XBUS, J4, J5, J6, J13, J14, as any card that stacks on top would have female headers matching the locations of jacks.

[barnacle]

I've been amusing myself...
- I think all the connectors are on 0.1" centres, but I might have missed some
- I've moved all the components to the front, purely for aesthetic reasons, but it would be cheaper to produce
- I've shifted the rom downwards so there may be space for your ZIP socket. The A17 header might be in the way.
- I've improved things under the processor _a lot_; it's much tidier now.

Still a couple of areas to tidy: top right of the processor, and to the left of the processor. And possibly a copper fill around the regulator to help get rid of heat.

Neill

[Martin_H]

Neil, I like your new layout, but I can't keep up with you. It took me quite a while to implement your last set of ideas. I figure the A17 header could be used as a solder bridge as well. That way it wouldn't be in the way of a larger socket.

[barnacle]

Heh. You are under absolutely no obligation to use my (or anyone else's) suggestions They're purely something I've done to while away a couple of afternoons, and in the hopes that you might find the ideas useful. (I've never had a layout described as 'elegant and attractive' before: thank you!)

I do second Bills point about 0.1" centres. For DIP or SOIC IC packages, and for imperial pin headers, that's a no-brainer. However, it's not absolutely essential: for a stacking board project I would tend to make a PCB design with just the headers and the corner holes in the places I want to put them, no other components, and copy and paste that design into my actual working drawings. That way, everything aligns automatically, 0.1" or not.

There's always an itchy feeling putting an imperial grid on a metric board; there are very few cases where things line up exactly and 100x100mm ain't one of 'em. My habit is to start with the board cuts, usually 100x160, and put 3.2mm holes 4mm in from each edge. If I'm using flood fill power, I usually start that at 1mm from each edge. Only then do I switch to imperial measurements with an 0.1" grid with the origin centred bottom left to place pin headers and ICs; then switch to 0.025 or 0.0125 for routing.

But remember what I said earlier: select a component _pin_ before positioning it, rather than by its centre.

Neil