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Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Mon Sep 29, 2014 2:45 pm
by ElEctric_EyE
Random 8x8 characters seem functional.
Code: Select all
LDX #2047 ;plot 2048 random ASCII characters, during HSYNC, using HDL PRNG for Character Plot Function
rock LDA rng
STA color ;foreground color
LDA rng
STA bcolor ;background color
LDA rng
AND #%0000000000111111 ;[7:0] bits is ASCII value, only 96 characters available so mask off [5:0]
ORA #%0000000100000000 ;set bit [8] to 1 for C-64 font
STA Att
NG LDA rng ;get 16-bit sample from HDL pseudo random number generator
AND #%0000011111111111 ;mask off 11 bits
CMP #1920-8
BCS NG ;if random sample is >1911 get another random sample
STA cX
NG1 LDA rng
AND #%0000011111111111 ;mask off 11 bits
CMP #1080-8
BCS NG1 ;if random sample is >1071 get another sample
BCF0C $FFFFE ;Branch if Control Flag 0 is Clear (0). CF0 is HSYNC input, so branch to itself and wait until hsync = 1, a non display period
STA cY ;plot Character!
DEX
BNE rock
imp JMP imp
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Mon Sep 29, 2014 5:53 pm
by ElEctric_EyE
Random Rectangle Fill function has been fixed.
Code: Select all
LDX #49 ;plot 50 rectangles using PRNG and Fill Function
rock LDA rng
STA color
NG LDA rng ;get 16-bit sample from HDL pseudo random number generator
AND #%0000000011111111 ;mask off 2^8 bits for 256 pixel width
CMP #256
BCS NG ;if random sample is >255 get another random sample
STA fXlen
NG1 LDA rng
AND #%0000000011111111 ;mask off 2^8 bits for 256 pixel height
CMP #256
BCS NG1 ;if random sample is >255 get another sample
STA fYlen
NG2 LDA rng
AND #%0000011111111111 ;mask off 2^11 bits
CMP #1920-256 ;subtract max width to make sure it fits
BCS NG2
STA fXs
NG3 LDA rng
AND #%0000011111111111 ;mask off 2^11 bits
CMP #1080-256 ;subtract max height to make sure it fits
BCS NG3
BCF0C $FFFFE ;Branch if Control Flag 0 is Clear (0). CF0 is HSYNC input, so branch to itself and wait until hsync = 1, a non display period
STA fYs ;Rectangle Fill!
DEX
BNE rock
imp JMP imp
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Mon Sep 29, 2014 6:15 pm
by ElEctric_EyE
I just noticed in all the 65Org16 software I've been posting there is a glaring mistake. But Bitwise's As65 automatically takes care of the error. The error is
It must have been truncating the highest hex value so an incorrect
results in an correct
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Wed Oct 01, 2014 11:22 pm
by ElEctric_EyE
I've been trying abit of software that utilizes the Square Root Function and the Plot function of the simple LineGen accelerator. I've tested the Square Root Function on a few numbers for Xs and Ys and it appears to work in simulation. It takes 2 16-bit registers named Xs & Ys, squares them both then performs the square root mathematics according to Jack Crenshaw's formulas. You can read about that
here.
Code: Select all
8/26/2014 smg Programming the 16-bit 2D Graphics 'LineGen' Accelerator
FUNCTION...............VARIABLE = 'description'....................R(ead)/W(rite)
________________________________________________________________________________
Line Generator............color = pixel color..........................RW
lx0 = X position start.....................RW
ly0 = Y position start.....................RW
lx1 = X position end.......................RW
ly1 = Y position end(*)....................RW
Rectangle Fill............color = pixel color..........................RW
fXlen = Horizontal length....................RW
fYlen = Vertical length......................RW
fXs = X position start.....................RW
fYs = Y position start(*)..................RW
Pixel Plot................color = pixel color..........................RW
Xp = X position...........................RW
Yp = Y position(*)........................RW
Read Pixel Color.............Xr = X position...........................RW
Yr = Y position(*)........................RW
colordata = 5-6-5 16bit R-G-B color data.........R
Copy & Paste Rectangle....bXlen = Horizontal length....................RW
bYlen = Vertical length......................RW
bXc = X position start of copy.............RW
bYc = Y position start of copy.............RW
bXp = X position start of paste............RW
bYp = Y position start of paste(*).........RW
Character Plot............color = pixel color..........................RW
bcolor = background pixel color...............RW
Att = ASCII character + font...............RW
(0000000axxxxxxxx. xxxxxxxx = 8bit ASCII)
(a = 1 C64, a = 0 DOS. FONTS)
cX = X position...........................RW
cY = Y position(*)........................RW
SIN LUT Generator........Xblock = (0..15) BRAM LUTs for X coordinates..RW
Yblock = (0..15) BRAM LUTs for Y coordinates..RW
Xoffset = placement within 1920 Horizontal.....RW
Yoffset = placement within 1080 Vertical.......RW
xfreq = # of SIN repetition within LUT1......RW
yfreq = # of SIN repetition within LUT2......RW
Xphase = (0..1023) Phase input to LUT1........RW
Yphase = (0..1023) Phase input to LUT2(*).....RW
Square Root Generator........Xs = 16bit number.........................RW
Ys = 16bit number(*)......................RW
Root = SQRT(Xs^2 + Ys^2)....................R
________________________________________________________________________________
NOTES:
(*) This Verilog Hardware Function is initiated after a write to these registers.
----------------------------------------------------------------------------------------------------
HMMM, I just noticed, no more color effects when posting here. I was trying to highlight the used functions...
So, this is the software that attempts to plot the first quadrant of a circle.
Code: Select all
LDY #100
STY RADIUS
LDX #0
NX STX Xs
STX Xp
STY Ys ;SQRT!
LDA Root ;Root = SQRT(Xs*Xs + Ys*Ys)
BCF0C $FFFFE ;Branch if Control Flag 0 is Clear (0). CF0 is HSYNC input, so branch to itself and wait until hsync = 1, a non display period
STA Yp ;PLOT!
INX
CPX #100
BNE NX
imp JMP imp
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Thu Oct 02, 2014 9:40 pm
by ElEctric_EyE
Woops. I realized the SQRT formula is incorrect as I need a Y value to be calculated for every X and Radius, so the HDL should perform a SQRT(Rs*Rs-Xs*Xs), i.e. Y=SQRT(R^2-X^2). I'll fix this and also use the Character Plot routine to plot out the X, Y and RADIUS values on the screen.
I can see it is still not a correctly plotted quadrant of a circle.
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Sun Oct 05, 2014 12:48 pm
by ElEctric_EyE
Fixed the SQRT function, it was looping 1 cycle too many for 'i'. Also now it doesn't shift the result in cycle CALC6 like in the
old version.
Code: Select all
//SQRT state machine
SQRTINIT:
state <= CALC3;
CALC3:
state <= CALC4;
CALC4:
state <= CALC5;
CALC5:
if (i != 14)
state <= CALC3;
else state <= WAIT;
Code: Select all
//square root generator
SQRTINIT:
begin
LGREADY <= 0;
i <= 0;
rem <= 0;
Root <= 0;
a <= Rs*Rs - Xs*Xs;
end
CALC3:
begin
Root <= Root << 1;
rem <= ((rem << 2) + (a >> 30));
end
CALC4:
begin
a <= a << 2;
Root <= Root + 1;
end
CALC5:
begin
i <= i + 1;
if (Root <= rem) begin
rem <= rem - Root;
Root <= Root + 1;
end
else Root <= Root - 1;
end
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Sun Oct 05, 2014 1:23 pm
by ElEctric_EyE
Simple program to draw 1 quadrant as X goes to radius.
Code: Select all
LDA #%1111100000000000 ;red pixels
STA color
LDY #100
STY RADIUS
LDX #500
STX TEMP2 ;x position of characters
LDWi $0000 ;LDW #$0000. character Y position
LDX #0
NX STWzp TEMP ;STW $0009. y position of characters
STX Xs ;Xs starts at 0 and goes to radius
STX Xp
LDY RADIUS
STY Rs ;SQRT! Halt the cpu, calculate and put value in Root.
LDA Root ;Root = Y = SQRT(Rs*Rs - Xs*Xs). From: R^2 = X^2 + Y^2
BCF0C $FFFFE ;Branch if Control Flag 0 is Clear (0). CF0 is HSYNC input, so branch to itself and wait until hsync = 1, a non display period
STA Yp ;PLOT Pixel! Halt the cpu and plot.
plot_hex ;MACRO. plot hex value in A accumulator starting @ coordinates (TEMP2,TEMP).
INW ;
INW ;
INW ;
INW ;
INW ;
INW ;
INW ;
INW ;add 8 pixels for plotting on next line
INX
CPX RADIUS
BNE NX
imp JMP imp
I don't like it.... Y value is shown in hex. I'll have to revisit variable diameter circles later. Need to push on!
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Sun Oct 05, 2014 6:22 pm
by ElEctric_EyE
6 functions are tested here. The software is well documented, trying to do myself a favor for future viewing. Pix to follow soon.
Code: Select all
;----Draw Green Border. Purpose: Test +-dx vs +-dy Line drawing-----------------
LDA #%0000011111100000 ;green pixel for a Border
STA color
LDA #0 ;from top left to top right
STA lx0
STA ly0
LDA #1919
STA lx1
LDA #0
STA ly1 ;Draw Line!
STA lx1 ;from top left to bottom left
LDA #1079
STA ly1 ;DRAW Line!
STA ly0 ;from bottom right to bottom left
LDA #1919
STA lx0
LDA #0
STA lx1
LDA #1079
STA ly1 ;Draw Line!
LDA #1919 ;from bottom right to top right
STA lx1
LDA #0
STA ly1 ;Draw line!
;----Plot 4 Characters. Purpose: Test Read/Modify/Write on register Att.........
LDA #%0000000000000000 ;setup pixel color for character
STA color ;plotting
LDA #%1111111111111111
STA bcolor
LDA #$21
ORA #%0000000100000000 ;set bit for C-64 font
STA Att
LDA #1
STA cX
STA cY ;!Plot Char 'A'. top left
INC Att
LDA #1079-8-1
STA cY
INC Att ;!Plot Char 'B'. bottom left
LDA #1919-8-1
STA cX
LDA #0 ;!Plot Char 'C'. top right
STA cY
INC Att
LDA #1079-8-1
STA cY ;!Plot Char 'D'. bottom right
;----Plot Character String. Purpose: Show all available Characters & Fonts------
LDX #10
STX cX
LDY #200
LDWi $0000 ;LDW #0
cont_plot LDAaw CHARSTRING ;LDA CHARSTRING,W
CMP #$0D
BEQ JOB
SEC
SBC #$0020 ;make ASCII compatible
ORA #%0000000100000000 ;set bit for C-64 font
STA Att
plot_string
INW
BNE cont_plot
JOB LDA #%1111111111111111
STA color
LDA #%1111100000000000
STA bcolor
LDX #10
STX cX
LDY #209
LDWi $0000 ;LDW #0
cont_plot2 LDAaw CHARSTRING ;LDA CHARSTRING,W
CMP #$0D
BEQ JOC
SEC
SBC #$0020 ;make ASCII compatible
ORA #%0000000000000000 ;clear bit for DOS font
STA Att
plot_string
INW
JMP cont_plot2
CHARSTRING .BYTE "ABCDEFGHIJKLMNOPQRSTUVWXYZ abcdefghijklmnopqrstuvwxyz 0123456789 !@#$%^&*()_+-=[]{}\|;',./<>?", $0D
;----Copy/Paste. Purpose: Test hardware copy/paste function---------------------
JOC LDA #100
STA bXlen ;length of horizontal copy/paste
LDA #10
STA bYlen ;length of vertical copy/paste
LDA #0
STA bXc ;copy start X coordinate
LDA #200
STA bYc ;copy start Y coordinate
LDA #900
STA bXp ;paste start X coordinate
LDA #200
STA bYp ;BLIT! paste start Y coordinate
;----Read color of pixel. Purpose: Read color of a pixel and use value for Fill-
LDA #%000000000011111 ;blue pixel
STA color
LDA #60
STA Xp
STA Yp ;Plot!
LDA #60
STA Xr
STA Yr ;Read!
LDA colordata
STA color ;
LDA #32
STA fXlen
LDA #32
STA fYlen
LDA #150
STA fXs
LDA #100
STA fYs ;Fill rectangle with read color
;----Plot Line. Purpose: Test Line Drawing Max Range----------------------------
LDA #%1111100000000000 ;red
STA color
LDA #0
STA lx0
STA ly0
LDA #1919
STA lx1
LDA #1079
STA ly1 ;draw line from top left to bottom right
geck JMP geck ;end
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Sun Oct 05, 2014 7:08 pm
by ElEctric_EyE
Not so good with the camera! Pixel rate is 150MHz. Monitor expects 148.5MHz for 1920x1080. Could explain apparent ghosting of pixels? I will test..
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Sun Oct 05, 2014 8:27 pm
by ElEctric_EyE
Limited fun with LUT's:
Code: Select all
;----Generate sine wave from 10-bit LUT. Add pixel, phase and BRAM offsets.-----
;----Draw lines from the center and trace the sinewave.-------------------------
;----Display xfreq = 1.-------------------------------
LDA #%1111111111111111 ;white pixels
STA color
LDA #0 ;[0-15] 1K BRAMs
STA Xblock
STA Yblock ;(not used here)
LDA #0
STA Xoffset
LDA #0
STA Yoffset ;plot at top right
LDA #1
STA xfreq
LDA #1
STA yfreq ;1 is minimum for frequency
LDA #0
STA Xphase ;sin
LDA #256 ;256/1024= 1/4 out of phase for circle
;generation using (x(sin),y(cos))
STA Yphase ;Generate 2xLUTs! cos (not used here)
LDX #0 ;draw a line from the center of the
;sinewave to the sinewave Y coordinates.
LDA #1024/2 ;
STA lx0 ;
LDA #1024/4 ;
STA ly0 ;from the center
liner TXA
STA lx1
LDA scratchx1,x ;read sin data from BRAM pointer Xblock #0
STA ly1 ;PLOT line!
NC INX
CPX #1024 ;
BNE liner
grock JMP grock
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Sun Oct 05, 2014 8:45 pm
by ElEctric_EyE
Code: Select all
;----Display xfreq = 5.-------------------------------
Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board
Posted: Tue Oct 07, 2014 11:50 pm
by ElEctric_EyE
Ok, so I think this is going to be the final test. I could've pushed further for 3D stuff, especially with 3 boards which seem to work flawlessly but I've been reading of some new IC's which has advanced some and I want to put my hands on it and integrate it into my controller board.
Controller board next, or new PVB design? I'm
was torn but I think the decision has been made. There is some angst because either design will be designed around a BGA package.
Logic tells me design a new PVB around a larger BGA Spartan 6 with 2 SyncRAMs. A new design, but I know what to expect from these RAMs. Delay will be at least 4 months.
Logic also tells me stick with the boards that are now functioning and design the controller board around the larger BGA Spartan 6. I think this is the way I will go, this will also take about 4 months, but the PVBs are already in place Ready, Willing and Able to do my bidding.
This last test I'm happy with, it's nice and fast. It simulates an oscilloscope by a sweep from left to right using the hardware accelerator PLOT! during HSYNC and a rectangle FILL! during VSYNC to clear the waveform when it reaches the end of screen. I'll post a video soon. Here's the software:
Code: Select all
;----simulate oscilloscope------------------------------------------------------
LDA #%0000000000111111
STA TEMP ;dynamic range of signal
LDA #1080/2
STA TEMP2 ; position of scope trace, close to middle of the screen
bg LDA #%0000011111100000 ;green pixels
STA color
LDX #0 ; x position start
PHX ; push for the value of zero, needed for a fill
loop STX Xp ; set X value for PLOT
LDA rng ; get 16-bit number from PRNG
AND TEMP
CLC
ADC TEMP2 ;set PLOT for middle of screen
BCF0C $FFFE ;Branch if Control Flag 0 is Clear (0), CF0 is HSYNC input, so branch to itself until hsync = 1, a non display period
STA Yp ;PLOT!
INX
CPX #1919
BNE loop
PLX ; get a quick zero from a previous push
STX color
STX fXs ; X position start for FILL
LDA #1920
STA fXlen ; horizontal length for FILL
LDA TEMP
STA fYlen ; vertical length for FILL
LDA TEMP2 ; Y position start for FILL
BCF1C $FFFE ;Branch if Control Flag 1 is Clear (0), CF1 is VSYNC input, so branch to itself and wait until vsync = 1, a non display period
STA fYs ;FILL! clear previous 1920xTEMP waveform
JMP bg