6502.org

I see Arlet is hard at work with his video core in his new update! Now he has bitmapped sprites!

I've had limited time to read parts of UG393 I've mentioned a couple posts ago as far as where it says to placebypass caps, and what values to use. I'm confident in my power distribution system for the FPGA so far. The PDS is of primary concern for the FPGA now. Things learned will funnel down to the other IC's present on the board...
I do plan to add 1 or 2 more via's where the 2.5V and 1.2V go into the FPGA power planes from the voltage regulators at the bottom of the FPGA. This should have the effect of lessening the transmission line impedance, thereby lessening noise even further, if I understand the datasheet correctly...

Next on this PCB agenda:
1) add wires for the Spartan 6 to the XCF04S Prom and 6-pin SIP JTAG connector.
2) add wires for the video CS4954 to the Spartan 6. Address decoding almost ready.
3) make custom footprints of RCA, S-Video, PS2, & 1/8" audio jacks/connectors. Also make footprints for SMD oscillator, jumpers, & 48-pin QFP.
4) I know there's something I forgot
5) add bypass cap's to the VR's

It only required adding 5 more lines of verilog. The only problem is that my internal data path is 32 bits, while the pixels are only 16 bit. The transparency logic is done by gating the write enable in the 32 bit path. So I either show 2 solid pixels, or 2 transparent pixels at a time.

To support single transparent pixels, I need read-modify-write logic instead, which is possible, but a bit more complicated (especially since it still needs to be single cycle). The same 32 bit path also means the X-position of the sprites must be 32 bit aligned, which means that you can't put the sprites on odd X coordinates. It's possible to fix that with a separate alignment unit in the data path.

Arlet wrote:
...It only required adding 5 more lines of verilog... It's possible to fix that with a separate alignment unit in the data path.

How long did it take you to write that 5 lines of code though?...
And I'm sure you'll figure out a logical compromise for the sprites.
ElEctric_EyE wrote:
...
Next on this PCB agenda:
...
4) I know there's something I forgot...

Placing the SDRAM wires is what I forgot to mention. It's actually what I started to do this morning and I'm almost done.

Before when I looked at a 144-pin QFP package I was overwhelmed by all the pins. Now I am learning what to focus on for an actual design beginning, before a schematic is even made, for inside the FPGA: The User IO pins, this is what to focus on. And they become sparse very quickly on a 144-pin QFP, especially when large 16-bit wide SDRAMs are involved. Multifunction pins can be used, but are discouraged at early design stages according to UG393, but I've already used a few VREF multifunction pins in Bank 3 and Bank 0 (the left and top sides of the FPGA)...
Needless to say, I am being very cautious at this early stage, very cautious. All GCLK's are being preserved for a situation calling for a GCLK and are not being used/multiplexed for say an address or data bus IO...
A 'design does not fit' error must not because of a pin that is locked, when it shouldn't have been...
This is a primary reason to keep this mainboard simple.

Progress report:

SDRAM wired in.

JTAG almost fully wired in. It's a little different than a Spartan 3 JTAG I was hoping to simply copy over from my 6502SoC. For example, the CCLK of the Spartan 6 needs a Thevenin parallel termination, according to Note 3, bottom of Pg. 24 of UG380. This means an added 2 resistors compared to the Spartan 3 JTAG interface. I'm putting in SMT 0603 resistor pads that are present in both designs, also you can see from the diag on Pg. 24 not all resistors are spec'd. If a resistor is not needed, I'll just solder in a 0ohm resistor, but this will require a little troubleshooting. No problem .

Relocated some parts...

Replaced 2 pin power in connector with a 4-pin connector (to accomodate power from a typical desktop PC switching power supply, i.e. 12V,GND,GND,5V), and added a 12V tap.

Also, one of my ideas is to have a jumper to hardwire select from the FPGA, either the onboard SDRAM CS or an offboard SRAM CS. This will figure into the (soon to be present) expansion connectors on the upper-left and top-left of the board.

The 14-pin DIP socket which was going to house a user 1/2 or full size can oscillator, is going to disappear in favor of a SMD 100MHz 3.3V HC/TTL oscillator.

Lastly, if you want to see the latest up-to-date main board layout, just click the link on my sig.

ElEctric_EyE wrote:
...Also, one of my ideas is to have a jumper to hardwire select from the FPGA, either the onboard SDRAM CS or an offboard SRAM CS...

Still thinking about this, it may be possible. Both the current SDRAM and a $7 10ns 256Kx16 SRAM would need 37 pins. I think I will focus on this next: Drawing the pins out to a suitable connector system. I'm still looking for a better solution than the 10-pin SIPs I have pictured now...

Wired in the SMT oscillator. Still have to make it jumperable to select an outside frequency source. Looking for suitable jumper headers...

Finished the XCF04/JTAG interface today. BTW, I am favoring a cheap $12 parallel JTAG3 interface cable anyone can purchase from DigilentInc, or just make their own. But the 6-pin SIP will follow this form from top to bottom:
1)TMS
2)TDI
3)TDO
4)TCK
5)GND
6)VCC (1.8V-5.5V)

I made the JTAG interface very flexible becase I don't know 100% about JTAG, so I must cover all my bases. If a resistor is not needed, then a 0ohm can be soldered in, also all external pullups can be from VCCAUX(2.5V) or VCCO(3.3V)...
One detail that is different from the Xilinx Datasheet, which spec's a TDI/TDO path from JTAG->FPGA->PROM->JTAG, is my TDI/TDO path is from JTAG->PROM->FPGA->JTAG. It gives the PROM precedence over the FPGA. This config I cannot jumper, which is why I mention it here. Not sure if it's a big deal, but I do believe I borrowed some parts of a Spartan 3 Digilent board schematic, as not all of Xilinx Datasheet's made sense to me at the time I was writing up schematics for the the 6502SoC.
Also, I forget where now, but I do believe I had read somewhere someone was having a problem with iMPACT software recognizing his devices using JTAG after having had followed the Xilinx specs. I thought it was Mike from FPGAARCADE, but not him as I read his entire homepage looking for the reference... Though, nice work he's doing over there in Sweden.
Anyway, I mention all this stuff about JTAG, just in case anyone happens to look at the layout and say "what the heck is that?". They are just my feedback resistor/power supply jumper options placed on the board, in the form of 0603 pads. I intend to do the testing, and will place the resistors/jumpers...

Was also working today on drawing out all the unused GCLKs and unused multifunction pins. Man it is tight in there! I only got bank3, the left bank done so far.
Also, there are 2 dedicated I/O pins in bank 2 (bottom of FPGA) that I plan to connect to a mini-PS2 keyboard connector. The rest of the unused multifunction pins in bank 2 will be drawn out to a connector.

Does anyone know if a 54-pin TSOP-II can fit (any size) SMT cap's directly underneath the package and pins still be solderable?
If I can move the bypass caps's from underneath the SDRAM (on the opposite side of the board), to directly underneath the SDRAM package (i.e. I would solder caps first, then place the device on top), it will free up alot of space in that corner of the board. Maybe fit 2x 2Mx8 10ns SRAMs

I'm checking clearance info...

There's supposedly a max of .006" under there, so no. One sheet I checked is at http://www.st.com/internet/com/TECHNICA ... 004731.pdf . Another one from another company agreed.

Hi Garth,

What's the difference between .006 and .009?

Searching Digikey for .006 thickness SMT cap's led to maybe 1 or 2 very expensive choices...

Search Digikey for .009 thickness SMT cap's, and you'll see a much larger selection...


I think the solder would still flow...

I went off on a tangent again sorry, but the SRAM memory IC's wouldn't have fit with all the traces wired on this 3.8x2.5" board, even if the bypass cap's were to fit underneath the SDRAM IC's.

A couple of major changes I am making to the present layout:

Gonna lose the 3.3V regulator. As the power supply is meant to by supplied by a typical PC power supply, 3.3V is readily available at a larger amperage already, starting to push over 1 Amp already for the 3.3V supply... Also, 5V is there too, for the PS2. Will have to find a decent power connector, maybe 6 pins.

The orientation of the entire JTAG section will be rotated 90 degrees left. This will put the JTAG connector towards the top middle left of the mainboard while also keeping the PROM and jumpers/caps in close proximity to the FPGA.

All of the output connectors will be soldered underneath the mainboard, this includes the audio & video. PS2 input connector also will be underneath. This will clear vertical space for a close fitting 2nd board. Also, all buttons will be right angled, and we'll have to see where they can fit.

The I/O connectors I have my eye one to interface a plug-in board are here. They have a much tighter .050" spacing, and when placed very close to a board edge there is no way to sneak traces through the neighboring pins. No problem. We can still fit alot more signals on the side facing the FPGA/SDRAM in a smaller area compared to a .100" spaced header... The side facing away, maybe use about 3 pins on the outer edge to wrap around. The other "trapped" pins can and will be used for power transmission.

ElEctric_EyE wrote:
...The orientation of the entire JTAG section will be rotated 90 degrees left...

Hah, sounds easy, but I had to redo the entire JTAG section in order to position it correctly. I also started wiring in the expansion connectors. 1 step closer to finish!

Wiring to the 2 expansion connectors are complete. It did require rerouting a few JTAG signals, so JTAG is not complete as stated before...

All signals from the FPGA to onboard SDRAM and the offboard expansion SRAM connectors have been completed. 1 more expansion connector at the bottom, and 1 video IC, and a few odds and ends, and maybe a month or two we should have a Spartan 6/video board ready to implement the 65016, or anything else for that matter.

I retract my last statement of expecting 1 or 2 months to completion. I made much progress the last 2 days.

JTAG is complete.
All expansion female interface headers are complete.
VR/all bypass cap's complete.


Only things left to complete are the audio filter and some pins on the Cirrus 4654.

I must keep total holes <=350 for this board according to the $98 MiniBoard 4-layer service. I am already trimming the power transmission holes/pins from the headers (H1, H2 & H3) to meet this requirement...
This will require a separate power supply connector to any additional boards.

...Rounding off the video section with the Cirrus 4954 in control of the S-Video connector, I've added a female RCA connector that is jumperable to choose between the 4954 composite out or the typical HSync/Vsync/pixel data (through onboard resistors), giving the user the option to generate their own video signals from the FPGA. Chris has a nice tutorial on this.

I keep having to trim holes!
Using SMT buttons now, saved me 8 more holes. Wired up audio, S-Video and composite video out connectors. I have to wire in the reset and program buttons Then I am DONE! Then I must double and triple check, then I will order the boards. I can almost taste them.

It is complete!

I couldn't fit a low-pass filter for the audio out.

All IC's/components/connectors are wired and stuffed into a 3.8" X 2.5" 4 layer MiniBoard.
I added a 6 pin .050" connector (K6) to experiment with. It has VGA signals present. Whether they're compatible or not with a VGA monitor remains to be seen.

I will finalize a parts list next, then finalize the schematic.

Hi EEye
just a thought: those 3 headers you have as partially-populated. If they are through-hole parts, to mount them you'll need to remove some pins or drill some holes. Or do you have another plan? Or have I missed something?

Cheers
Ed