6502.org

The only difference between the old and new from the 6502's point of view is the clock divider in register 2. The old device had a 6 bit clock divider which would slow down PHI2 for the SPI shift clock. For me, I always had is set to 0 and a few times to 1. There were not enough resources in the ATF1504 to have this divider. So in the new device, register 2 and 3 both access the Slave select outputs.

A write to bit 2 (ECE) of register 1 (SPI Control register) will select either PHI2 if low or the external clock pin source if high.

I hope this answers your question. I will work on updating the user manual to reflect these changes.

Thanks!

Daryl

Good news! Jacco from the Netherlands has done some testing with the ATF1504 version of 65SPI. I had made a few logic errors in the initial version that he encountered but we have worked through them and I have updated the source and JED files. I believe basic operation now parallels the older Xilinx 65SPI, with the exception of having the clock divider removed.

Jacco's implementation is running at 2MHz while 4MHz does not work. It is unknown if his his test rig is limiting the clock speed or if the ATF is not as fast as the Xilinx. He may do some more testing but I believe he has done enough to prove the logic code conversion now works.

You can read more and download the manual, source, and JED file from my website https://sbc.rictor.org/65spi2.html

Many thanks to Jacco for sharing his findings with me and being willing to test my revisions!!!

Be safe!

Daryl

Hi Garth,

I do not plan to provide pre-programmed chips at this time. My hobby time is too limited. If I can find more time, I will try to add details on how to program your own. If anyone else has already done this, then please share what hardware and software you are using.

Thanks!

Daryl

(There's a writeup here of (re)programming an ATF1504 CPLD using OpenOCD. Dave/hoglet has a recipe for using a Raspberry Pi with OpenOCD here (That's a 3V recipe...))

Thanks Ed!!

Is there a particular reason why the BSY bit is bit 5 instead of bit 6? It seems to me it'd be much more useful to be able to check BSY quickly with BIT than IER.

I have not really used the BSY flag in my past applications. The port is usually in an idle state when you enter the driver code so you would make the initial write and then you can poll the TC bit for completion.

Having said that, your question is a good one and your reasoning is valid. I will switch the IER and BSY flags in the status register and also move the IER bit in the control register to bit #5, to keep them aligned.

Thanks for your feedback!

Daryl

My pleasure testing it out, Daryl!

I programmed my ATF1504 after reading an Instructable by a guy called Doctek:
https://www.instructables.com/id/Ghetto ... ent-Syste/

He points towards an easy to build version of Altera's ByteBlaster for old parallel ports, so i built that.
Then used ATMISP on an old XP laptop to program it with Daryl's JED file.
Was a piece of cake, really.

Now on to the quest for speed.
I was testing, mainly, with a GameDuino clone (Olimex MOD-VGA32) that claims to accept up to 8 MHz SPI clock.
Alas it maxes out with me at 2 MHZ, but that might be due to the voltage conversion i need to do.
(The thing runs on 3.3v and is not 5v tolerant!)

Hi all,

I have made one last update to the 65SPI v2. https://sbc.rictor.org/65spi2.html

Control register bit 7 now provides a software reset. Writing a 1 to that bit will reset the device. Setting any other control bit high during the same write will override the reset default for that bit and set it high.

I want to recognize and thank Jacco again for helping me to iron out the conversion from Xilinx to Atmel and for helping to keep the 65SPI viable! Jacco also provided a proven and inexpensive method for programming the Atmel ATF1504AS!

Best wishes to all - and be safe!

Daryl

Just in case if anyone is interested. XC9572 (recycled chips) is still readily available from AliExpress. I've purchase 10 for few USD and wired a breadboard to program the 65SPI v1. I had hack the PLCC44 to DIP40 adapter that I have to make sure all the VCC & GND pinout are connected. I installed the latest ICE Webpack for Windows 10 and using Impact to program the JED file to the XC9572. It seem to program/verify fine. I will get it into my 6502 build soon.

I'm not familiar enough with WinCUPL to understand the 65SPI design, so I re-draw it into Altera schematic so I can visualize it better. Altera also have better optimizer so it should compile more efficiently with Quartus. Can someone review the schematic to see if I've captured it correctly?

BTW, the design compiled OK. Macrocell utilization is 83%
Bill

Hello Bill,

Nice work. That looks like it took a long time to create. I will look it over later tonight and let you know if I find anything.

Daryl

I'm used to design CPLD in schematic. Like assembly language, I found schematic more efficient than high level design language. I'm confused about the precedence of operators in WinCUPL, so I'm guessing that:
!D0 & CS1 & !CS2 & PHI2 & !A1 & !A0 & !RW # SRES;
is same as
(!D0 & CS1 & !CS2 & PHI2 & !A1 & !A0 & !RW) # SRES;

and
!st0 & !CPHA # st0 & CPHA
is same as
(!st0 & !CPHA) # (st0 & CPHA)

The other uncertainly is Altera's flip flop symbol has inverted asynchronous reset and asynchronous preset. So I added an inverter output to all your equations for async reset & preset.

I also used short hand representation for buses, array of gates, and array of flip flops. So you may find the array representation of shift registers and control registers confusing. If so, I can draw them out as individual flip flops.

Bill

Hello Bill,

Yes to the precedence question. And I can follow the shorthand/bus logic, so no need to redraw. I got caught up with family activities last night so could not review this as I had planned. I'm working on it now and should have a response shortly.

Daryl