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PostPosted: Tue Feb 06, 2007 9:51 am 
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Well, Samuel, if you read through this whole thing, you are to be commended. I can't imagine that very many people will. It would be good if there were an easy way to diagram some of this for posting, but I've already spent too much time at it as it is. Writing it however made me confront a bunch of issues I was probably trying to ignore before, hoping they would just work out ok. By posting this, I hope to get good ideas and even have potential problems pointed out. If I don't get the feedback, I guess I'll go ahead with the plan, starting with hardware for the workbench computer's mezzanine.

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A MAX765 can provide a -12V regulated supply given a 12V input, at what appears to be 250mA output current. That translates to 3W of power. I'm assuming that there is a similar MAXIM chip that provides a +12V regulated supply also at 250mA; that's a total of 6W of power. Will ribbon cable be able to deal with that kind of power?

How big is ribbon-cable wire? #26? #26 copper wire's current capacity is about 350mA (fusing current is about 20A!), and it has about 41 ohms per thousand feet. (I might reach a max of 10 or 20 feet for this.) If anything needed the kind of power you're talking about, I would expect it to have its own power supply and not rely on power that the controller supplies.

Although I have plenty of twisted-pair ribbon here left over from a job I did 15 years ago, I thought I better look again at the twisted-pair ribbon cable I gave you the link for. I see it uses #28 wire, not #26. This initially seemed like bad news because it means less current-carrying capability. But OTOH, the maximum safe current, according to a different book (not the one where I got the 350mA earlier for #26) is 830mA for #28, or 1.4A if in free air. Fusing current is 14.4A, and resistance is 72 ohms per thousand feet. The first book said only 227mA for #28 @ 700 circular mills per amp. I have no idea how they chose 700cm/A as their reference, or whether it is a good reference point.

Anyway, I usually want at least two conductors for ground, because if you have just one and it goes intermittent or something, there's a chance it could mean damaged equipment, not just temporary non-op. I also went for two +12V lines in the proposed connector pinout above, but only one -12V since that one is not as critical and generally does not have to carry as much current anyway. The two workbench computers shown on my project pages are usually run at the same time, and I've never seen the pair of them plus anything attached to them take more than maybe 200mA (combined) from the +12V line, even though the 5V regulators on the computers are 7805 linear instead of efficient switchers. The -12V is usually somewhere around 30mA.

If the higher voltages were absolutely not available from the master, a pair of pin headers could be connected to a power supply in order to power up the SPI bus. As far as any data issues go, it would be invisible and transparent. It seems like a neater solution than having auxiliary power connectors on all the low-power bus devices.

But what kind of power supply are you using that makes +12V (or anything close-- even 9V) hard to come by? How about a Jameco cat. no. 162996 12V (regulated) 500mA wall-wart for $11, or their no. 154624 Motorola-made 5V@.5A,12V@.13A,-12V@.13A regulated table-top 3-output power supply with 8-pin mini-DIN output plug for $13? That's the cost of less than 8 feet of the 16-conductor twisted-pair ribbon cable.

About the microcontroller-gated 74xx125 clock- and data-line buffers that pass signals between the main bus and a sub-bus: The clock line in particular needs a bus-holding device so it can't change state and foul things up if you have to pause a long SPI transaction to take care of an interrupt or other SPI need in the middle. (Just having a pull-up or -down resistor may not do the job correctly, depending on things like SPI mode.) The '125 has four sections. Three are used for clock, MISO, and MOSI. The fourth section can follow the clock buffer section, be enabled full time, and have a 47K resistor from its output back to its (CMOS) input to produce the bus-holding device. When the output of the main clock buffer is disabled, the resistor will give the positive feedback needed to maintain the last state.

The master should have weak pull-up resistors in the range of 22K to 47K on all lines (except IRQ\) that it does not drive to a valid logic state at power-up before the port is set up by software. The IRQ\ line has a 3.3K pull-up at the master. For IRQ\ many microcontrollers offer at least one pin that can be used as an open-drain output, allowing wire-ORing without external parts. MISO of course is never driven by the master, but I'd rather not leave the master's MISO input floating. Another possibility is to use a bus-holding device, a buffer with light positive feedback as discussed above. Pull-down resistors would rule out any of the bipolar (non-CMOS) 74-family logic since pulling their inputs to a logic low take a lot more current than pulling up, and in fact they tend to pull up to a valid logic-high input state if left unconnected. I don't plan for bipolar logic (like 74LS) to be used regularly, but sometimes I use it in a pinch late at night if it's all I have and the local electronics supply stores are closed. With the input-protection diodes on CMOS parts, the weak pull-up shouldn't ever cause any damage to non-powered-up devices.

As far as SPI modes go (for review, see viewtopic.php?t=636&start=31 ), since I'm going to bit-bang through a 65c22, I can handle any of the modes or even Microwire (although Microwire's active-high CS inputs need inverters ahead of them-- arrrgh) or dumb shift registers or other things that are close but don't necessarily match any official SPI mode. (We talked about that earlier. It's unfortunate that it's not all uniform, but we can live with it. At least it's always msb-first.) With the pull-up resistor on the clock line, I propose having the hub and intelligent front-end microcontrollers operate on SPI mode 3, meaning clock high when the µC's slave SPI port's SEL line goes true, and data clocked on rising edge. Modes 0 and 3 seem to be most common, and the PIC microcontrollers' SPI port operates in mode 3 when the CKP (ClocK Polarity) control bit is a 1. CKP=0 puts it in mode 1, ie, idle clock low, data clocked on falling edge. A front-end µC's config array could include the info on the mode used by the SPI device it hosts, although to talk to that device, the master will have to know all about it anyway.

In thinking through the details, this issue of SPI modes turned out to have a lot of implications for sub-bus operation that frankly were a big pain. I think I've gotten most of the potential problems solved. Let me know what others you think of.

For the master to communicate with a device on a sub-bus:
  1. 1. De-select everything on the master's SPI bus (but not necessarily other sub-buses).
  2. Set initial SPI mode-3 clock state (high) for the hub.
  3. Select the hub.
  4. Send the hub the one-byte instruction to set the proper sub-bus SEL line true. Note: The hub will not select the specified sub-bus device yet however, but it will know to wait for the next time the master selects the hub. This allows the master to set up the initial clock state for the sub-bus device's SPI mode before the sub-bus device's SEL line goes true, and without "confusing" the hub with an extra clock edge.
  5. De-select the hub.
  6. Set up the initial clock line logic state appropriately for the sub-bus device.
  7. Select the hub again. It now knows not to listen to the master, but to just enable the buffers, and, immediately after that (2µs is enough), set the appropriate sub-bus SEL line true, and then quit listening as the master and sub-bus device communicate.
  8. Master communicates with the sub-bus device.
  9. If necessary, you can interrupt the communication this way:
    A. De-select the hub. This disables the buffers and retains the last clock signal logic state. Remember this state to restore when we resume communication.
    B. Take care of the interruption (not involving this particular sub-bus).
    C. Come back and re-select the hub. Go through the above sequence again, without ever de-selecting the sub-bus device you want to resume communication with. Going through the sequence again is necessary for getting to the point where the hub lets you through to the sub-bus device and tunes out while you resume your communication. For this, restoring the previous data line state (mentioned in 9A above) may need to be added to #2 above.
  10. When the master is finished communicating with the sub-bus device, de-select the hub. The hub will disable the SPI buffers from the main SPI bus to the sub-bus.
  11. Set the clock line high (mode-3 initial state) and re-select the hub and tell it to de-select all sub-bus devices (instruction $10).

I don't think anything here precludes the nesting of hubs, but I'll need think think it through more thoroughly when my head is more clear.


Configuration and polling protocol: I would expect that in most cases, the microcontrollers for hubs or intelligent front ends can all be the same, even in software, except that their data array would reflect differences like what kind things it can do (is it file-oriented like a disc drive, or graphics-display-oriented like a graphics LCD module, or...), speed limits, model number, serial number, etc.. The most-read things should come first so you can get them without reading the entire array if you don't want to. For the basics, I propose a format something like the following.

With the exception explained in #4 and #7 above, the first byte the master sends out after selecting a hub or front-end µC is always an instruction for the µC itself, not instructions or data for sub-bus devices. If that byte is in the range of 01 to $0F (remember-- a dedicated hub that's internal to a piece of equipment with multiple SPI devices can have more than 6 or 7 devices on its sub-bus), it means to enable the buffers and assert the corresponding SEL line on its sub-bus after the µC sees its slave SPI port's SEL line go false and then true again, as detailed above. When the µC does this, it will tune out until it is de-selected and then selected yet again. "Tuning out" means not only ignoring incoming data, but also setting its MISO line to high-impedance so there's no bus contention. Instruction $10 means immediately negate all SEL lines on the sub-bus. (00 is a dummy instruction that I'll get to in a minute.) No "turn off buffers" instruction is needed, because the µC does that unconditionally when its SEL line goes false anyway. $11 could be a request to send the config array. I haven't really gotten that far yet, as I don't seem to need it as much as you do.

The µC's slave SPI port's SEL input also goes to another interrupt-on-change input pin if necessary so that with minimal response time, the µC can load the sub-bus's interrupt status into its SPI output register, so that as the master shifts the instruction into the µC, this interrupt status byte is shifted out for the master to read at the same time if it's relevant. If all you want to do is read the interrupt status, you send the 00 do-nothing instruction to the µC. This scheme allows interrupt polling without transferring more than a single byte. Even one bit would be enough if it's the first one shifted out and you deselect the µC before finishing 8 shifts (an entire byte). This allows very quick polling to find the source of an interrupt. Some µCs may need to reset their slave SPI port if the SEL line goes false before 8 clock pulses are received. According to the data book, the PIC16C62 I plan to use looks like it will not automatically start over when it is selected again, so I'll have to make the software reset the SPI port when its SEL line goes false. A front end or non-dedicated hub will only have one interrupt input from the sub-bus. If a hub claims responsibility for an interrupt, you may have to poll individual devices on its sub-bus to find the source of that interrupt if there's more than one interrupt-enabled device. There will never be more than 7 interrupt sources on the sub-bus. The first bit shifted out (msb) tells if anything requested interrupt. In the case of a front end or non-dedicated hub, that's as far you need to look. But in the case of a piece of equipment with its own internal dedicated hub to service multiple SPI devices, the remaining bits tell which device made the interrupt request, like reading the IFR of a 6522. Without talking directly to the devices on the sub-bus, you can tell the dedicated hub which devices you don't want interrupts from by sending it a $12 instruction with an operand byte that works like writing to the IER of a 6522. The dedicated hub µC can have an input pin for each device on its sub-bus so it knows which device produced the interrupt request.

So far I don't foresee any instruction sent by the master to a hub or front end needing more than one operand byte. If there is such a need, I wonder if it would be ok to plan on those being terminated by negating the µC's SEL line. Sending data the other direction, the only time I can think of that requires more than one byte per answer is when the µC sends the config data array, which can start with a length byte and again the master has the option of cutting it off (by deselecting) before reaching the end. Any other info I can think of asking the hub itself is something the controller should remember anyway, like "Which sub-bus device do you have selected?" The answer of course is "Device X, just like you told me, remember?"

I don't think anything here stands in the way of making your own SPI devices with a microcontroller. If you make such a device, it will be the device and the intelligent front end all in one.

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PostPosted: Wed Feb 07, 2007 4:19 am 
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GARTHWILSON wrote:
Now as I write, these two topics (including the "small-connector version" topic) say they've had 1546 views. It would be interesting to know how many others have been quietly reading and just have not felt they had anything to contribute.

I've been reading the thread. How much of it I'm actually remembering is another story. :) Anyway, I don't have a need for a (new) serial bus currently, or for the foreseeable future either, so I haven't responded simply because I haven't really given the topic much thought.

When forum activity is low, I'll often read all the (updated) threads, even those where I have minimal interest and/or knowledge. I almost always sign in ONLY to reply, so I'm not sure how much (if at all) the "view" count gets inflated by all this reading without signing in.


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PostPosted: Wed Feb 07, 2007 5:37 am 
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If the higher voltages were absolutely not available from the master, a pair of pin headers could be connected to a power supply in order to power up the SPI bus. As far as any data issues go, it would be invisible and transparent. It seems like a neater solution than having auxiliary power connectors on all the low-power bus devices.


I've decided on implementing the +12V supply rails on the bus for the Kestrel 2; however, I'm not planning on implementing the -12V. I'm going to leave that pin open. Maybe on a later generation of hardware design . . .

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But what kind of power supply are you using that makes +12V (or anything close-- even 9V) hard to come by?


An off-the-shelf 5V wall-wart that I happened to have in my junk box.

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How about a Jameco cat. no. 162996 12V (regulated) 500mA wall-wart for $11, or their no. 154624 Motorola-made 5V@.5A,12V@.13A,-12V@.13A regulated table-top 3-output power supply with 8-pin mini-DIN output plug for $13?


Listen to yourself! You sound like QVC!! :D

The reason I've decided to go with the +12V supply is because the FPGA board, I now realize, requires 9V input supply. And, I figure, I could rig up an LM317T to linearly produce 9V from a 12V supply. And if I've got that, then I satisfy my requirement for 12V on the SIB.

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About the microcontroller-gated 74xx125 clock- and data-line buffers that pass signals between the main bus and a sub-bus: The clock line in particular needs
. . .
clock buffer is disabled, the resistor will give the positive feedback needed to maintain the last state.


Hey, I never thought of this idea. I was thinking originally of using pull-up or pull-down resistors instead. But, this is a better approach. Thanks for the tip!

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A front-end µC's config array could include the info on the mode used by the SPI device it hosts, although to talk to that device, the master will have to know all about it anyway.


Unless the microcontroller can (somehow) perform mode translation.

Here's a question: will an SPI device of mode Y respond if communicating to it in mode X? The reason I ask is because, if it doesn't, then it's possible that we can just poll the bus 4 times, one per mode.

If this is a problem, though, then the front-end will always need to operate in a consistent mode.

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I don't think anything here precludes the nesting of hubs, but I'll need think think it through more thoroughly when my head is more clear.


I'm curious -- what if you don't know the state the hub is in? Sending an address byte may inadvertently go to the peripheral currently addressed, rather than the hub controller. How do you reset the link to a known-good state?

This is why I prefer to use a single select to perform both device addressing and data transfer. When SEL goes negated, then everything is known to be in a reset condition, ready for the next transaction.

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$11 could be a request to send the config array. I haven't really gotten that far yet, as I don't seem to need it as much as you do.


I'm planning on a COM-like approach here. A peripheral exposes one or more interfaces to the master, and it makes sense for the master to query the peripheral for its capabilities based on certain vague expectations. For example, while booting the computer, the Kestrel really only cares about two things: keyboards and boot devices. Any other peripheral can be detected and told to go into a default state, but beyond that, no inherent support will be offered. This also prevents the problem that is **SO** often found in Linux, where a new hardware card comes out, and it's chipset compatible with something else (e.g., EtherPro 100-based chipset used in some third party card). But because the PCI configuration values are different from Intel's, the card is "unsupported," and Linux doesn't see it, despite the fact that the driver inside the kernel works just fine with it.

With Linux, it's not quite so bad a problem as it would be in Windows because we can hack the source to the driver. But, now your drivers must independently maintain (sometimes huge!!) lists of PCI vendor and card IDs.

No thanks. The peripheral should be as self-identifying as possible. Sure, it'll have IDs and model #s and names and stuff. But more importantly, it'll offer a single interface by which the MASTER asks the peripheral (not the other way around!) actively, "Hey, do you support the Network command set?" "Hey, do you support the disk I/O command set?" Etc.

The inspiration for this comes from Microsoft's COM (Component Object Model), which maps perfectly to this application. In doing this, I only need to maintain specific interface IDs based on my goals, not based on the entirety of the peripheral market space. :)


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PostPosted: Wed Feb 07, 2007 5:39 am 
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dclxvi wrote:
When forum activity is low, I'll often read all the (updated) threads, even those where I have minimal interest and/or knowledge. I almost always sign in ONLY to reply, so I'm not sure how much (if at all) the "view" count gets inflated by all this reading without signing in.


I believe the view counter increments on any view at all, regardless of whether or not you're currently signed in.


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PostPosted: Wed Feb 07, 2007 8:51 am 
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I may need to think about some of your points some more, but I'll give the easy answers here quickly as that should be helpful.

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I'm not planning on implementing the -12V.

If it's neither supplied nor needed, no big deal. STN LCDs usually have a negative voltage for the backplane though, the cheaper line drivers use it, and a lot of ananlog work will use it for things like data converters and accompanying op amps.

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Listen to yourself! You sound like QVC!! :)

Is that the home shopping network? (I tried Wikipedia on that one.)

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Unless the microcontroller can (somehow) perform mode translation.

I've used PICs for a lot of products we've sold, again for all the reasons except their horrid processor core. There are sure a scad of varieties, but I'm not aware of any with more than one synchronous serial port (SSP). Maybe that Scenix that lordsteve was recommending, or some other high-performance µC, could be used to bit-bang at good enough rates to detect the mode and translate between one bit-banged port and another. The most stringent real-time requirement comes in by the fact that data is shifted out at the same time as in, and you'd have to have significantly less than half a shift clock's delay.

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Here's a question: will an SPI device of mode Y respond if communicating to it in mode X?

A small percentage of devices will do a limited amount of auto-detection, but I think that otherwise the answer is that they'll just be off by one clock and really foul things up, or half a clock and be trying to latch data when it's changing to the next state. At best, I think set-up and hold times might get you in trouble.

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The reason I ask is because, if it doesn't, then it's possible that we can just poll the bus 4 times, one per mode.

If the wrong modes don't do something like write garbage over a part of EEPROM, or overvoltage something on a programmable power supply, then that might work fine. For myself, I'd have to be satisfied that I won't wind up with one of these problems.

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I'm curious -- what if you don't know the state the hub is in?...

Just select and de-select it a couple of times without transferring any data, and it will be ready for instructions. This is similar to getting control back on I²C bus from a device that's hung up for some reason and doesn't want to release the bus. You just give it 9 clocks without pulling the data line low for the acknowledge at the end of a byte it's sending (wherever the end is, even if unknown) and it'll let go.

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This is why I prefer to use a single select to perform both device addressing and data transfer. When SEL goes negated, then everything is known to be in a reset condition, ready for the next transaction.

Hopefully my answer above will satisfy; but what you're saying is indeed what I originally planned. It was the issue of the different modes that threw a wrench in the monkeyworks. You can't just change modes for the sub-bus device and then tell the hub "Ok, turn on the buffers now" since the mode change leaves the hub unable to understand anything other than its SEL line. I considered using specific delays, but there were too many potential problems. The toggling of the SEL line seemed to be a much better solution after I realized how easy it is to recover from not knowing what state it's in.

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I'm planning on a COM-like approach here...<snip>

I have no disagreement with your four last paragraphs there, but it's kind of a foreign field to me. I suppose my serial number idea was just so the master can tell the difference between two of the same that are plugged in; but in the case of mass-storage, it could tell from volume labels anyway. The 1-Wire interface uses serial numbers so for example you can have a dozen identical temperature sensors in 3-pin TO-92 packages on the same line and distinguish between them. (I haven't paid much attention to 1-Wire though. It has semi-stringent timing requirements to make it possible to merge the clock and data lines, and there's not nearly as much available in 1-Wire as there is in I²C or SPI.)

What you want to do will require adding more intelligence than anything I have in mind does. I don't think that will make it incompatible with what I have in mind, as long as everything doesn't need to have this intelligence, but I'm afraid I can't contribute much on that part of the discussion unless your let-me-run-this-by-you's also educate me so I can comment. We seem to be well on our way to a good interface spec if it allows this kind of plug-and-play for the things you mention while also allowing the quickly put-together experiments I need to be able to do-- the whole range. If we want others to adopt it, they will have to be able to stop at whatever level of complexity suits them and their needs, and be comfortable with that.

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PostPosted: Wed Feb 07, 2007 5:08 pm 
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Component Object Model (COM) is an object/component technology that enforces (stringently) a distinction between an object's interface (what it can do) from its implementation (how it does it). The problem is, any given object can potentially do everything, or nothing at all. How does one find out?

COM requires that all interfaces implement a minimum of three methods: QueryInterface is used to probe an object to see if it can do something else, while AddRef and Release are used to manage the object's lifecycle in memory.

To illustrate how QueryInterface is used, consider what appears to be a normal file. You have a pointer to a file object, and it exposes the usual stuff -- you can read from it, write to it, query its file size, etc. But what if it's a special *kind* of file? For example, it could be a database table. If so, you ought to be able to send it an SQL database query. The file interface lacks this capability -- all it can do is read/write bunches of bytes. So, you invoke QueryInterface, asking if it supports the Database interface. If it does, you can then use that new interface reference to issue the SQL query. (Likewise, Database interfaces aren't necessarily all files either! Consider the case where you have a dedicated database server -- in at least some of the cases, therefore, Database objects can also be network connections. And in the case of JOINs, they could reside entirely in local RAM, with no backing storage at all.)

Hardware devices, unlike software objects, exists purely as singleton objects, so there is no need for AddRef or Release. Dropping the final reference to a device will not cause the device to suddenly vanish from your desktop with an audible *fffffPOP!* sound.

But, all devices ought to respond to a command equivalent to QueryInterface. For example, an MMC card reader clearly implements mass storage-like attributes and capabilities; thus, it ought to respond to the MassStorage interface. If the peripheral also supports its own filesystem implementation, as the Commodore disk drives to, then it ought to expose a FileSystem interface. Etc.

These things are determined by labeling each interface with a unique identifier. In COM and in my proposal, 16-byte unique IDs are used. These are 128-bit numbers called UUIDs, and the algorithm for their generation allows for such a high degree of uniqueness that it eliminates any overt need for a central registry authority or database.

Most UUIDs are tied to one of your network card's MAC address (and since those are unique at all times by necessity and by regulation of IEEE, it guarantees UUIDs are also unique). For those cases where it's not, UUIDs are generated via an MD5 cryptographic hash of various pieces of data that you offer it. The odds of me offering the same pieces of data as you are very, very small -- thus, the odds of a collision, while non-zero, comes asymptotically close to zero.

In your example, you said that $12 would cause the device's configuration profile to be sent. I propose $13 to be able to ask the device for whether or not it supports a given interface. If it does, it will return a successful indication, along with instructions on how to access that facility. The precise manner of how this is done is not yet fleshed out, so I can't go into more details at this time. If it does not, it just returns a message saying, "No."

By adopting a scheme similar to this, you end up writing class drivers instead of device drivers as such. Class drivers (a term I borrowed from USB documentation) are basically device drivers that can address a whole class of compatible devices -- devices that willingly adopt a standard interface. HIDDs (Human Input Device Drivers) are class drivers, for example, that allow you to use virtually any USB keyboard or mouse with your computer. One driver module, thousands of peripherals.

This principle is, I think, important, because part of the Kestrel's goal is to allow the programmer the greatest functionality with a minimum of interference from system software and hardware. This is directly in line with how Forth is intended to be used as well. It helps to (sorry) "dispel the user illusion," but does so without sacrificing inherent capability.

Chuck Moore believes, and I vehemently concur, that it's easier to talk directly to the hardware than it is to talk to an operating system interface, provided that interface is standardized and not too complex (or, at least, the complexity is well justified). It saves 100% the code needed to implement the driver, if only the interface were standardized.

Commodore's serial and GPIB buses were used with this in mind. Devices were intelligent -- very intelligent. The only "driver" that Commodore's kernel had inside it was for the GPIB or serial bus. That's it. Literally all other code either touched hardware directly, OR, it issued well known and standardized command strings to other GPIB devices on the bus.

The "drivers" for a specific device, therefore, lay inside the peripheral itself, and quite often could run in parallel with the main computer, thus offering a degree of parallelism that PCs couldn't touch until Linux was generally available, decades later. I remember one metric used to guage multitasking on the PC was formatting a floppy disk while doing other things on the screen. The Commodore 8-bit line had the PCs licked in this area since 1977, and the kernel was never designed for multitasking. :) Simply send "N" to the disk drive's command channel, and then do something else.

I intend on capitalizing on this with the Kestrel. Maybe not upon first release, but eventually.

Now you know why this SIB is so much of interest to me.

Quote:
What you want to do will require adding more intelligence than anything I have in mind does. I don't think that will make it incompatible with what I have in mind, as long as everything doesn't need to have this intelligence, but I'm afraid I can't contribute much on that part of the discussion unless your let-me-run-this-by-you's also educate me so I can comment. We seem to be well on our way to a good interface spec if it allows this kind of plug-and-play for the things you mention while also allowing the quickly put-together experiments I need to be able to do-- the whole range. If we want others to adopt it, they will have to be able to stop at whatever level of complexity suits them and their needs, and be comfortable with that.


My system does not involve that much overhead. If you prefer to talk directly to SPI devices using their own protocol instead of a sanitized/regularized protocol, that's OK too. There are two approaches:

* Respond Yes to an interface query with the flag that it is a so-called "native SPI" protocol. Instructions would include which sub-device address to access it with, what SPI mode, what its timing parameters are, etc. In other words, it's just like reading a device's configuration file.

* Respond No to an interface query, and depend on the driver's innate knowledge of how to access the sub-device.


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PostPosted: Wed Feb 07, 2007 5:27 pm 
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I would like to humbly suggest the SX microcontroller as the microcontroller of choice for your serial bus initialization/handshake needs. I think it is exquisitely well-suited for that task. Yes, I am biased. All flavors are only $2.79 in quantities of 1.

http://www.parallax.com/sx/chips.asp

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PostPosted: Wed Feb 07, 2007 6:18 pm 
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But they are implementations of the PIC architecture, of which I'm vehemently against. Sorry.

The serial bus, by definition, couldn't care less what microcontroller you use on the other end, as long as it adheres to the protocols of the bus. I'm an ardent ATmega supporter. Although more expensive, I'm willing to pay that price for not requiring a frontal lobotomy to understand its instruction set and architectural limitations.

Realistically speaking, a 65xx microcontroller would work just as well, if only it supported SPI (I don't believe it does, if I recall correctly). It is the slowest of the bunch, but the most powerful and expressive overall.

And, the ultimate ideal, would be a MISC processor.


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PostPosted: Sat Feb 10, 2007 9:44 am 
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I would like to humbly suggest the SX microcontroller as the microcontroller of choice for your serial bus initialization/handshake needs. I think it is exquisitely well-suited for that task.

lordsteve, I don't know if you've been reading the whole topic which has been long and probably not easy to follow for someone who hasn't developed their own needs for this kind of thing in their experience, but I mentioned your SX recommendation above for hubs and intelligent front ends:
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Unless the microcontroller can (somehow) perform mode translation.

I've used PICs for a lot of products we've sold, again for all the reasons except their horrid processor core. There are sure a scad of varieties, but I'm not aware of any with more than one synchronous serial port (SSP). Maybe that Scenix that lordsteve was recommending, or some other high-performance µC, could be used to bit-bang at good enough rates to detect the mode and translate between one bit-banged port and another. The most stringent real-time requirement comes in by the fact that data is shifted out at the same time as in, and you'd have to have significantly less than half a shift clock's delay.


I have a couple of reservations about using a µC for the bus master itself however. It sounds like what Samuel wants to do will always be doable with a standard SPI port which apparently the SX28 has (although there doesn't seem to be anything at all in the entire 51-page data sheet about how to use it). OTOH, in this process of trying to define the bus, I've run up against scenarios in my own work where I occasionally need to interface parts that don't adhere totally to SPI standards. The data sheet for a given part may say "4-wire serial interface" or "3-wire serial interface" and not "SPI" because it truly is not quite SPI. It's close enough however that I can put it on this bus if I can have the tight bit-twiddling control that I probably can't get from a dedicated SPI port. If necessary, the SX's SPI port can be turned back into regular I/O bits on the fly (if it's like the PICs) for bit-banging; but the efficiency plummets because now I have to bit-twiddle through the SX's parallel slave port (if it even has one, which the possibly incomplete data sheet does not say anything about). Not having direct access to the I/O registers and other registers like we have on a 6522 makes for an awkward, slow method of getting the details through. I've run into this kind of thing before when considering any kind of multi-processor system. When the satelite processors know how to do their job and the communication between processors doesn't take long compared to the job they have to do, there can be a great performance benefit. But if it takes more effort for the main processor to tell the coprocessor what to do than it takes to just do it itself, the advantage is lost. In one of the other threads on multi-processor systems, I asked how to do the programming such that the administrative overhead of dealing out the jobs doesn't forfeit more performance than we had hoped to gain. I didn't get any responses.

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* Respond No to an interface query, and depend on the driver's innate knowledge of how to access the sub-device.

Does this still mean a non-intelligent SPI device can't sit directly on the bus without an intelligent front end because it doesn't even understand the interface query and know how to answer "No"? If so, we'll need to have different levels of the interface, similar perhaps to specifying that a particular ANS Forth program requires the optional "Locals" (or other) word set. Although much of what you're saying above is pretty foreign to me, what I understand of it sounds very good. I certainly don't want to stand in the way of what you seem to be trying to do with the Kestrel. I like it. I doubt that you'll like this solution, but it seems to be getting harder to accommodate the two extremes of the range from dumb devices to the ones you're talking about. Ideas? Do we need another line in the cable for a device to pull down meaning "I'm intelligent" when its SEL line goes true, so the master can find out without sending out initial polling bytes that could potentially be damaging with a non-intelligent device misinterpreting them?

This community will be writing all the code to interface anything we use, whether that code goes in the master or the device's front end. For me, with the interactiveness of the workbench computer's development system and the fact that it's 6502 (or '816), it's much quicker and easier to develop code that executes on the workbench computer instead of the device's intelligent front end. OTOH, if I got equipment from someone else, it might be preferable to get the driver code already incorporated in the equipment's front end instead of getting software for the master in a form I was not set up to handle. There will be many episodes of my own use before that equipment-sharing scenario becomes reality though.

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PostPosted: Sat Feb 10, 2007 10:48 am 
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GARTHWILSON wrote:
In one of the other threads on multi-processor systems, I asked how to do the programming such that the administrative overhead of dealing out the jobs doesn't forfeit more performance than we had hoped to gain. I didn't get any responses.


Couldn't find this thread, so if you post the link, I'll answer :-)

André


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PostPosted: Sat Feb 10, 2007 11:04 am 
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if you post the link, I'll answer :-)

I guess it was viewtopic.php?t=217


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PostPosted: Sat Feb 10, 2007 5:57 pm 
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In most situations where you have a "job processor" and a bunch of slave processing nodes, the job processor is a completely separate system unto itself. Administrative overhead is therefore overlapped with the slave processor's activities, and thus doesn't impact the performance gains from the system.


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PostPosted: Sat Feb 10, 2007 6:09 pm 
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GARTHWILSON wrote:
Does this still mean a non-intelligent SPI device can't sit directly on the bus without an intelligent front end because it doesn't even understand the interface query and know how to answer "No"? If so, we'll need to have different levels of the interface, similar perhaps to specifying that a particular ANS Forth program requires the optional "Locals" (or other) word set.


I'm sorry, but I thought that this was already established as a given. You clearly stated in an earlier post that you wanted to be able to specifically isolate devices as being too dumb to respond to autoconfiguration properly.

I
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deas? Do we need another line in the cable for a device to pull down meaning "I'm intelligent" when its SEL line goes true, so the master can find out without sending out initial polling bytes that could potentially be damaging with a non-intelligent device misinterpreting them?


Well, I already proposed that a device could have two overt addresses. Besides MISO, MOSI, CS, CLK, and IRQ, there would also be a CONFIG pin. The "configuration engine" is selected when (CS AND CONFIG) is true. The "peripheral proper" is selected when (CS AND NOT CONFIG) is true.

If all you have is a dumb device, then simply leave the "configuration engine" out of the circuit. The total lack of response within a given timeframe (say, half a second) from a peripheral's configuration engine means it's a dumb device.

The disadvantage is that it consumes "yet another pin" on the serial port (as does your "I'm Intelligent" feedback pin).

This is precisely why I was saying above, you EITHER have that explicit ability to address two sides of a peripheral (with one side potentially being deaf-mute if it's not supported), OR, you must always have an intelligent front-end processor (even if only a stub) for consistency. Otherwise, you run into situations where the computer cannot enumerate the bus without fear of really jacking something up in the process in the event it's a dumb device, leading to solutions such as "exclusion lists," where you identify, a priori, which devices are not smart enough to enumerate. To me, that defeats the purpose of auto-configuration support, but with only 6 devices to 7 devices per port, it's livable. :)


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PostPosted: Sun Feb 11, 2007 1:29 am 
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You're right. A couple of times since we started the thread, I've re-read it from the beginning, but I forgot about the CONFIG pin for a couple of reasons: before I understood where your plan was headed and how important it was to you to have everything pollable whether it can respond appropriately or not, I thought we had met the need without dedicating another pin, on page 2; but now I see there's something I missed even back then, not to mention that there's just a lot to remember on this thread. Do you want to go back to the CONFIG pin?

Quote:
Well, I already proposed that a device could have two overt addresses. Besides MISO, MOSI, CS, CLK, and IRQ, there would also be a CONFIG pin. The "configuration engine" is selected when (CS AND CONFIG) is true. The "peripheral proper" is selected when (CS AND NOT CONFIG) is true.

It means I'll have to add a gate to the simplest devices so they won't be selected when CONFIG is true, but I can live with that. I'd sure like to use a different scheme so the extra gate (a transparent latch) would go on the smarter devices instead of the simplest ones, but I guess I can't really justify it. Here's how it would work: The configuration selection involves asserting the appropriate SEL line, then asserting CONFIG, then negating the SEL line, using CONFIG to keep an intelligent device's SEL status "latched" until CONFIG is negated. That keeps the simplest dumb devices from being required to have the gate, because when they're selected, the clock will not get toggled until after their SEL line goes false again.

I guess the sub-buses' CONFIG would get set through commands to the hub.

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The disadvantage is that it consumes "yet another pin" on the serial port

So are we back to a slightly bigger connector, like a 20-pin IDC? That still beats a 26-pin. If there's no other way, I'm willing to go for it to get the maximum range of usefulness. I was considering a couple of things:
--> Five SELect lines may not be enough if we forfeit another one for the CONFIG line. The bigger connector will let us get from six back up to seven and still get the CONFIG, while pairing a couple more lines with grounds (or virtual grounds).
--> Similar situation with the -12V that I sometimes need. If it were derived at the device, the easiest way to get a negative voltage from a positive one is with an inductorless switched-capacitor charge-pump voltage converter. Very few can handle that kind of voltage, but the Linear Technology LT1054 can go to 15V input and deliver enough current for what we've talked about. Still, putting one converter on the master is easier than having to put one in every device that needs it.

Thanks for pointing out the MAX765, as I may use that for something else; but there are a couple of reasons I would not recommend it here. The 765 skips pulses at low load currents in order to be more efficient. This pulse-skipping produces more output ripple on lower frequencies, which will be fine for line drivers and LCD backplanes, but is not suitable for any audio work. Also, these things are not hobbyist-friendly. Take it from someone who has designed these things into commercial products. The first time we used one, I put the MAX732 12V step-up switching regulator on a 6-layer board with ground plane. The 732 only runs at 170kHz so it's already a little easier to design a board for. (Remember that the dI/dt of a switching regulator even at 170kHz is very, very high, and the effect of parasitic inductances on the board and component leads becomes huge.) Still, it was a bear to get the layout right so the part would operate smoothly and not have excessive output ripple at frequencies below the switching frequency. A couple of years into production, Maxim "improved" the wafer-fab process, making the switching faster, and giving us trouble again at high harmonics of the switching frequency. Since we had tons of these multi-layer boards in stock, we opted to do some hand modification since that was cheaper than throwing out otherwise-good boards. We had to solder a capacitor directly to the IC leads with almost no lead length (try getting production people to understand that!), scrape the soldermask off of a few other places and solder chip capacitors on (since chip capacitors have no lead length), and put ferrite beads over certain wires to keep RF noise out of the aircraft radios that operate in the 108-135MHz band. I used the same switching regulator again in other designs later, but by then I knew how to do it right and we didn't have any more trouble. (Part of that, BTW, involved the chainsaw line we talked about earlier.)

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The total lack of response within a given timeframe (say, half a second) from a peripheral's configuration engine means it's a dumb device.

There probably is no need for a timeout period since it's synchronous and the master dictates the data transfer rate.

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PostPosted: Sun Feb 11, 2007 2:33 am 
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GARTHWILSON wrote:
Do you want to go back to the CONFIG pin?


I think it's the most flexible solution, personally.

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That keeps the simplest dumb devices from being required to have the gate, because when they're selected, the clock will not get toggled until after their SEL line goes false again.


Slick! I hadn't thought of that protocol.

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I guess the sub-buses' CONFIG would get set through commands to the hub.


Remember that hub addressing can be done via the config engine on the hub; therefore, a "high level" command to select a device's config engine (as distinct from a device itself) is now possible, letting the hub itself handle the timing of the SEL->CONFIG->/SEL sequence you described. This might make things easier.

Of course, we're speculating. We won't know the real requirements for hubs until we actually run out of ports. :)

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So are we back to a slightly bigger connector, like a 20-pin IDC? That still beats a 26-pin. If there's no other way, I'm willing to go for it to get the maximum range of usefulness. I was considering a couple of things:


What kind of savings in cost are you looking at using a 16-pin IDC versus a 20-pin IDC?

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Still, putting one converter on the master is easier than having to put one in every device that needs it.


The 20 pin IDC ought to allow a pin for -12V, if I recall correctly.

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There probably is no need for a timeout period since it's synchronous and the master dictates the data transfer rate.


Correct; but I was referring to a lack of response from the peripheral at all. You'll probably want to poll the config engine of a device up to 3 times before moving on, just in case the interface is in a weird state on power-on. It *shouldn't*, but then, lots of things *shouldn't* happen in a computer anyway. :D


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