ATF15xx Verilog/VHDL using Quartus 13.0 SP1

[jds]

Jmstein7 wrote:

I guess I have good timing - this thread is alive! I've been trying to use Quartus II to demux a 65C816 (data and bank) using an ATF1504as 7.5ns, but to no avail. I switched to WinCUPL, but I feel like I'm banging my head against the wall. I'm sure people have done this before; but I just can't get my code to do it. Yes, it compiles without error. Then, nothing. I have my logic analyzer hooked up, and nothing coming out onto the data lines (or bank).

If it's any help I have done similar with Quartus II. Some Rockwell microcontrollers multiplex the address bus and data bus and have a signal called EMS to time the latch. This is the verilog I used, which was working correctly:

Code: Select all

reg a_reg[7:0];

assign a11 = a_reg[7];
assign a10 = a_reg[6];
assign a9 = a_reg[5];
assign a8 = a_reg[4];
assign a7 = a_reg[3];
assign a6 = a_reg[2];
assign a5 = a_reg[1];
assign a4 = a_reg[0];

always @(negedge EMS)
    begin
        a_reg[7] = D7;
        a_reg[6] = D6;
        a_reg[5] = D5;
        a_reg[4] = D4;
        a_reg[3] = D3;
        a_reg[2] = D2;
        a_reg[1] = D1;
        a_reg[0] = D0;
    end

I'm sure I could have made the code more compact, but this worked so I didn't mess with it.