Slower SRAM works but fast doesn't????

[dolomiah]

Quick heads up folks. I hear the concern regarding lazy write, but we've also discussed in the early part of this thread the importance of fully qualified read/write. Hence why I am putting that in place as part of an overall redesign, which luckily can still all be implemented with the two 74xx00 and one 74xx04 that I have already placed on the board. See attached - takes in to account the guidance re address for chip select and Phi2 for read/write enablement.

I did try inverting the clock as part of an earlier 'simple' test. Maybe I was doing something wrong, but it all went a bit haywire, not just for the 15ns SRAM. I don't have a non-inverting gate such as AND, so used 2 NOT gates. But folks thought 16ns or more delay might be too much hence I didn't pursue this further. However GaBuZoMeu did recommend properly qualified R/W.

So there seems merit in going this path and eliminate one of the notions which is that I am asking for trouble by tying /OE low and relying on /WE connected directly to R/W without Phi2 qualification.

Attached is my redesign, hopefully there is no clanger in there, as I will be mapping it to the NAND and NOT gates on the board and hopefully getting it working again soon.

[Chromatix]

Well, I've spotted at least one outright mistake so far, but I think you're taking the right approach now. In particular, the ROM is now being driven correctly.

In the I/O selectors, you could save at least one inverter by swapping over your uses of E3 and /E1. I haven't yet teased out whether the second inverter is still absolutely required as part of the RAM selector.

However, the RAM selector is clearly wrong; you try to calculate ~(A15 & ~A14) which would select $8000-$BFFF active low, but actually get ~(~(A15 & A14) & ~A14) which would select $0000-$3FFF as well. This would effectively punch a needless 4KB hole in your RAM mapping at $3xxx. All this is because you took your "A15" input from the wrong place for that gate.

Your calculation of ~(Phi2 & RW) is duplicated for the RAM chip; you could just reuse the /OE signal from the ROM and save one NAND gate.

In your delay analysis, you calculate the delay of /WE as 2 gates - but that is from the RW signal, which is less relevant than the delay from Phi2 transitions (it changes at about the same time as the address lines). When a signal is clock-qualified, it's wise to show the delays from both combinatorial and clock inputs separately.

I think it's also worth looking for ways to shorten the gate chain for the RAM selector, since that is still 4 gates after correcting the error I spotted. One way to do this is to ignore A14, and calculate (~A15 | ~A13 | ~A12) somehow - combined with the inverse of the ROM selector, that is sufficient to deselect the I/O space. Here we can take advantage of the fact that a NAND gate is effectively an OR gate given active-low inputs and active-high output.

You already have ~(A13 & A12) === (~A13 | ~A12) within your I/O selector; so feed that and the ~A15 you also produce there into a NAND gate and you have a 2-gate-delay active-low selector for your RAM chip - send that straight to /CS1. For the active-high CS1 selector, just copy the ROM /CE.

This not only saves you 2 gate delays, but possibly as many as 3 inverters and another NAND gate.

[BillO]

In addition, I would run the RAM /OE [!(Phi2 & R/W)] signal to the ROM /OE as well. Save another gate.

[Chromatix]

I actually did mention that...

[BillO]

Chromatix wrote:

I actually did mention that...

Yes, I see that now. My eye must have skipped over that line before - blame decrepitude...

[Chromatix]

With that said, my suggestion for the RAM selector might itself still be slightly wrong. I need to write this out and be sure of it.

[dolomiah]

Chromatix - that's brilliant, thank you for taking the time to go through this. The glaring mistakes were me trying to rush this last night, but the insight around swapping the '138 enable lines and also the RAM enables lines to reduce gates and delay, well that's just great. Not that I have worked through your logic around the RAM select yet - I am confident you're right, but let me check it for my own learning and understanding. I've already made the corrections to the design and the better '138 selection, will also update with the RAM soon and repost.

[BillO]

Chromatix wrote:

With that said, my suggestion for the RAM selector might itself still be slightly wrong. I need to write this out and be sure of it.

If the RAM is 0000-AFFF he needs it selected as A15 & !A14 & A13 & !A12

So if he ran A14 and A12 into 1 NAND then into RAM CS2 and ran A15 and A13 into another NAND then into /CS1 - would that should do it. The he would have only a single gate delay on RAM select.

[Chromatix]

Quote:

A15 & !A14 & A13 & !A12

That selects $Axxx and nothing else. You also need to select $0000-$9FFF.

Quote:

A14 and A12 into 1 NAND then into RAM CS2

That would deselect several ranges below $8000. The RAM chip logically ANDs the two selectors, after correcting for their logical polarities.

[dolomiah]

I'm working on this now, so another way to look at it is that RAM is anything not ROM and not IO:

RAM = ~(A15 & A14) & ~(A15 & ~A14 & A13 & A12) as Chromatix points out, A14 is cancelled out
so
RAM = ~A15 & ~A13 & ~A12

[Chromatix]

The solution I've just worked out on paper uses a total of 5 NAND gates and 3 inverters - so you could use two 7400 chips and ditch the inverter chip entirely. In detail:

Code: Select all

Phi2 ~& RW -> ROM /OE -> RAM /OE
Phi2 ~& (~RW) -> RAM /WE
A15 -> IO E3
A14 -> IO /E2
A13 ~& A12 -> IO /E1
A15 ~& A14 -> ROM /CE -> ~(RAM /CS1)
A15 ~& ~(IO /E1) -> RAM CS2

This has a worst-case gate delay of 3 from A12/13 to RAM CS2. The delay from A14/15 to RAM /CS1 is 2 gates. This is achieved by moving an inverter from the end of the I/O hole deselector chain and swapping the two selector lines; otherwise we'd still have a 4-gate delay from A12/13 to RAM /CS1.

These delays could be reduced further using a different selection of gate types, I think. In particular a 3-input NAND would work directly for combining A15/13/12 to /CS1, giving both of the RAM selector lines a 1-gate delay. If you had one 7400 (quad 2-NAND) and one 7410 (triple 3-NAND), that's still a 2-chip decoder - with a 3-NAND gate spare to boot!

Code: Select all

Phi2 ~& RW -> ROM /OE -> RAM /OE
Phi2 ~& (RW ~& RW) -> RAM /WE
A15 -> IO E3
A14 -> IO /E2
A13 ~& A12 -> IO /E1
A15 ~& A14 ~& A14 -> ROM /CE -> RAM CS2
A15 ~& A13 ~& A12 -> RAM /CS1

[BillO]

dolomiah wrote:

so
RAM = ~A15 & ~A13 & ~A12

That's not quite right either.

My trouble is doing the Boolean algebra to see the minimum # of gates.

RAM selection needs to be when !((A15 & A13 & A12) or (A15 & A14)).

It's just a matter of how that looks in a minimal hardware implementation.

[dolomiah]

Oops, I have messed up De Morgan's law in my earlier equations..

[BillO]

Okay, I think this will do it. It is basically what Chromatix suggested and I think he was right after much Boolean algebra.

You are left with a 3 gate delay on RAM select and a 2 gate delay on Ram /WE

Give it a once over and run a truth table - I may have made an error.

[dolomiah]

Great stuff guys - will cross check later. I'm a bit annoyed with myself, a degree in computer science, and hadn't sat down properly to work this out, I should have been able to suss this way back when I first did it!

Will report back over the weekend hopefully when I have checked and got the circuit implemented