6502.org

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74HC and 74HCT came out in 1982. I would use 74HCT. Its input levels are compatible with TTL levels (hence the "T"), but it takes a lot less current than TTL, and its wider-ranging output voltage is not a problem; in fact, 74HC(T)'s fanout is 10 LSTTL loads.

The gates with pull-up resistors might be open-collector devices like the 74LS06. Could it be possible that the oscillator also drives the crystal pins in an input/output fashion ? In which case open collector logic might be needed. 470 ohms is a fairly strong pull-up. The spec sheet does say the oscillator uses the crystal in parallel resonant mode.

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Hang on, if you're using a clock generator, you don't need to worry about resonance - and I thought you said that was your preference?

I would expect the pullups are needed, and are strong, because the expectation was that the inverters are TTL and don't pull to the rail. So if you choose a logic family which does pull to the rail, you can probably do without the pullups.

It might be important that the two inputs are driven as shown, which is to say with one gate delay of lag, so I'd suggest you do the same. Driving with an actual two phase clock might be worse, in this case.

You could try just connecting a timing crystal across the 2 XTAL pins without any extra components.

See the schematic from the MTX500/512.
NB The MTX is a Z80 system, but I don't think that makes any difference.

Hi folks. I have previously posted on this same thread quite some time ago, but have a stable working 65c02 and TMS9918a set up.

I have a 21.47727 Mhz crystal, struggled to get hold of a 10.738635 one - they seem to be difficult to find in the UK at least.

So I used that crystal as the master clock for my breadboard, fed in to a 74HCT161 counter and used Q1 and Q3 outputs to drive the TMS9918a (Q1) and 65c02 (Q3). In fact I use Q3 (approximately 2.68 MHz) as the clock for everything else as well as the 65c02 (6522, 6551).

The TMS9918 can be driven with an external signal, but needs clock signal and its inverse to be fed in to XTAL1 and XTAL2 - a NAND gate from a 74HCT00 achieves that for me so I get a clean non-overlapping Q1 and /Q1 signal.

I have never really understood what is going on with clock circuits - they seem to be the most analogue of all the sub-systems on my homebrew. So I followed various schematics on the internet (and this forum too).

Anyway, I attach a photo of the clock circuit, with a couple of annotations, hope it helps a little..

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Maybe connect A12 to G2B, so that you're only decoding a 4k area of memory Axxx for the VDP, instead of 8k (A000-BFFF) ?

IIRC the 9918 series only requires a couple of I/O ports. If you are using only a single active low output you could consider something like the 74HCT688 which has a ton more inputs than the '138. Useful for resolving address ranges down to a finer resolution.

This fellow looks to have successfully interfaced the 9918 with the 6502 on his SBC:

https://www.youtube.com/watch?v=9bIwD_OyiA4

Apologies if this is someone already here

If so, great work and love the white PCB.