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Re: Techniques for reliable high-speed digital circuits
Posted: Sat Jul 08, 2017 5:00 am
by dwight
Cooling reduces resistance but doesn't change capacitance
much.
Still running a processor at liquid nitrogen temperatures can
significantly speed a processor.
Dwight
AC parallel termination
Posted: Thu Feb 15, 2018 5:59 pm
by BillO
Hi All,
I'm planning to use 25cm of standard IDC cable for a bus structure that will be driven by AC logic. I also plan to use AC parallel termination.
Given the following data for IDC:
Impedance - 100 ohms
Propagation delay - 4.53 nS/M
And using the rule of thumb that the RC time constant for parallel termination should be at least 3 times the line delay:
Line delay = 4.53/4 = 1.13
-> RC > 3.9 nS
So if R=100 ohms then C > 3.9 pF
Does this sound about right?
Re: Techniques for reliable high-speed digital circuits
Posted: Thu Feb 15, 2018 10:47 pm
by GARTHWILSON
If you're referring to an AC termination where the capacitor in question is in series with the terminating resistor, 3.9ns/100Ω=39pF (not 3.9). 47pF or even 100pF should be fine, giving a slight AC performance improvement without much increase in power waste. If signals need to go both directions, you would need the terminations at both ends. For the ribbon cable to be considered a real transmission line, every signal line needs to be next to a line that's grounded at both ends, and preferably every other line is such a ground line.
Page 12 of the .pdf here (page 16 of the file) sheds a little light on this. National Semiconductor's AN-610, "Terminations For Advanced CMOS Logic," and National's article "Design Considerations" in their 1990 FACT (TM) Advanced CMOS Logic Databook, are helpful, but unfortunately TI seems to have dumped them when they took over National. I have nothing good to say about TI's technical helpfulness. I've had problems with them since I started trying to deal with them in the mid-1980's in my work, and the difference was the major reason I much preferred doing business with National; but then TI took over National. <spit>
Related topics on the forum are:
Bus termination... and
Bus amplifiers and terminators (page 2)
Re: Techniques for reliable high-speed digital circuits
Posted: Thu Feb 15, 2018 11:35 pm
by BillO
Doh! So much for my degree in math.
Thanks Garth. Yes I plan to ground every 2nd line in the cable.
We’re you ever able to look into why I’m not receiving any notifications?
Re: Techniques for reliable high-speed digital circuits
Posted: Thu Feb 15, 2018 11:41 pm
by GARTHWILSON
Were you ever able to look into why I’m not receiving any notifications?
I mentioned this to Mike and then forgot. My apologies. I'll get back on it. Make sure your email service is not treating it as spam. (Maybe you already mentioned that.) We had a similar problem on AnyCPU.
Re: Techniques for reliable high-speed digital circuits
Posted: Fri Feb 16, 2018 7:26 pm
by BillO
Were you ever able to look into why I’m not receiving any notifications?
I mentioned this to Mike and then forgot. My apologies. I'll get back on it. Make sure your email service is not treating it as spam. (Maybe you already mentioned that.) We had a similar problem on AnyCPU.
Just checked Garth. There is nothing on hotmail that seems to be set to stop it. But then again, it's hotmail - they do whatever they like to do.
I'll change to another email address not administered by the evil empire and see if that works b better.
QUery: Wich reference plane is preferred?
Posted: Tue Mar 20, 2018 3:24 pm
by BillO
Here is a nice document from TI on high speed layout considerations. Not sure if it had been linked to before...
http://www.ti.com/lit/an/scaa082a/scaa082a.pdf
In any case, I have a question for those more seasoned in this stuff.
Id you have a typical 4 layer board:
Signal
GND
Vcc
Signal
Is there a preferred reference plane (GND or Vcc) to run traces over, if you have a choice? In other words, for the layout above, is better to run traces om the top (closest to GND) or on the bottom (closest to Vcc) or does it not matter?
Oh, also ... I was talking with a guy I know recently about me little 14mHz 6502 project. He recommended two things to me. 1) make the board larger than required in order to have a wide margin around the circuitry to reduce impedance in the GND and Vcc planes. and 2) Use copper pours on both the top and bottom to further reduce impedance on the power supplies providing these copper pours completely enclose the circuitry by a wide margin (see attached image).
What do y'all think of these suggestions?
Re: QUery: Wich reference plane is preferred?
Posted: Tue Mar 20, 2018 8:45 pm
by GARTHWILSON
It'll take time to do it justice, but it looks like there's some good stuff in there.
In any case, I have a question for those more seasoned in this stuff.
Id you have a typical 4 layer board:
Signal
GND
Vcc
Signal
Is there a preferred reference plane (GND or Vcc) to run traces over, if you have a choice? In other words, for the layout above, is better to run traces om the top (closest to GND) or on the bottom (closest to Vcc) or does it not matter?
You probably won't have much choice. One layer will have to be mostly going north and south, and the other, east and west (so to speak). Once it's mostly in, you can start changing some traces and segments to minimize vias. If the edge rates compared to the board size are fast enough to matter, there should be a bypass capacitor from the ground layer to the Vcc layer right near the via. The principle is illustrated in Figure 14 and described in the surrounding text, although there they have multiple ground planes. Ideally, the Vcc plane serves as an AC ground plane just as much as the ground plane does, being bypassed with capacitors in all the right places; but it's not possible to have the bypass capacitors' connections free of inductance, unless you put the capacitor in the board, like I show at viewtopic.php?p=16095#p16095 . When you have a chance to move traces from the Vcc side to the ground side, that's probably good.
Oh, also ... I was talking with a guy I know recently about me little 14mHz 6502 project. He recommended two things to me. 1) make the board larger than required in order to have a wide margin around the circuitry to reduce impedance in the GND and Vcc planes.
That's to approximate the effect of a pair of infinite parallel planes, which, as I understand it, result in no inductance. If you have .020" between layers, having something like .100" from the most outlying traces to the edge of the planes should do the job. It's not like you need a half inch out there.
and 2) Use copper pours on both the top and bottom to further reduce impedance on the power supplies providing these copper pours completely enclose the circuitry by a wide margin (see attached image).
If you do what's in the paragraph above about approximating infinite planes, the impedance is already basically zero, or at least dwarfed by the impedance of the IC lead frames and bond wires. The pours won't add any benefit unless you have lots of vias from the edge of the pour to the ground plane, especially next to signal vias. You could look up "coplanar waveguide" and "via fence" but the speeds of current 65xx OTS parts don't warrant going to that extent. [Edit, four years later: There is a way to use them to supplement real planes; but if they're not done correctly, they can actually make things worse, according to experts in the field like Rick Hartley, Eric Bogatin, and Suzie Web whose lectures you can see on Altium's YouTube channel.]
Re: Techniques for reliable high-speed digital circuits
Posted: Tue Mar 27, 2018 1:17 pm
by BillO
Thanks Garth,
The board is the size it is for the convenience of fitting into the casing, so that's not an issue in this case. Thanks for the tip though.
I followed your process advice on changing traces and eliminating vias. I was able to shorten the over-all trace length by about 30cm and reduce the vias from 74 to 33. I spent another 10 hours pouring over it and was not able to see a way to eliminate one more via, so I guess 33 is it.
To even eliminate the 41 I did took some rather unusual pains (at least for me) to accomplish. They included tossing out a 74373 in favor of a 74573, using 74245s instead of 74244s (you can define their direction without flipping them around), redefining the pinout of the GAL and taking advantage of the fact the order of address and data lines going to RAM and passing through buffers and data registers is immaterial (not so with I/O devices and ROM - for obvious reasons).
It is unfortunate that the 6502 pin-out is so at odds with the pin-out of memory chips. That is the single largest contributor to the via count.
After reading some published info on copper pours, I have decided to pass on these. They can certainly cause more trouble than they solve in digital circuitry.
Re: Techniques for reliable high-speed digital circuits
Posted: Tue Mar 27, 2018 6:55 pm
by GARTHWILSON
It is unfortunate that the 6502 pin-out is so at odds with the pin-out of memory chips. That is the single largest contributor to the via count.
Remember that on SRAM, you can mix up the address lines, and you can mix up the data lines. This is the first tip in the "Tip of the Day" column I ran 17 years ago. (Wow how time flies!) You can do that with ROM too, but you'll need either a programming adapter, or you'll need to pre-scramble it in software before programming.
Re: Techniques for reliable high-speed digital circuits
Posted: Sun Apr 01, 2018 5:44 am
by barrym95838
Remember that on SRAM, you can mix up the address lines, and you can mix up the data lines.
This is a significant point, and needs to be repeated early and as often as necessary.
This is the first tip in the "Tip of the Day" column I ran 17 years ago.
Mike B.
Re: Techniques for reliable high-speed digital circuits
Posted: Sun Apr 01, 2018 6:24 am
by DerTrueForce
Trouble with that is that is that most SRAMs and EEPROMs use very similar pinouts(In DIP, at least, and mine use exactly the same pinouts), meaning that it simplifies the routing to put them right next to each other on the PCB.
If I did do that with the RAM lines, I would probably end up putting the ROM near the CPU, on the other side from the rest of the ICs, and do the routing just that part.
Re: Techniques for reliable high-speed digital circuits
Posted: Sun Apr 01, 2018 6:56 am
by GARTHWILSON
Oops—my apologies for forgetting to add the link. Thanks, Mike.
Again, you can scramble the ROM lines too. I made a programming adapter for a product we made from 1993-2006 or so. And if the computer board can write to its own EEPROM, there's no need for special adapters or software for that. It doesn't need to know or care that the lines are scrambled.
If this matter of scrambling lines goes any further though, it should be put in a separate topic, as it has nothing to do with techniques for reliable high-speed digital circuits.
Re: Techniques for reliable high-speed digital circuits
Posted: Sun Apr 01, 2018 1:32 pm
by BillO
Remember that on SRAM, you can mix up the address lines, and you can mix up the data lines.
This is a significant point, and needs to be repeated early and as often as necessary.
This is the first tip in the "Tip of the Day" column I ran 17 years ago.
Mike B.
Yes, I am aware of that. You'll even find it in my last post. But to DTR's post, it can sometimes be of limited use, unless you want to scramble your ROM too. In my case I was using it as an intermediary step that saved me a couple of vias and some trace length as I had the RAM between the ROM and the CPU, but I've since found it more advantageous to place the Rom between the RAM and the CPU. Still my best measures were substituting 7457Xs for 7437Xs and 74245s for 74244s. As well, using GALs as glue logic is a huge benefit as you can redefine the pin out as desired to improve routing.
Re: Techniques for reliable high-speed digital circuits
Posted: Sat Jan 26, 2019 3:08 pm
by BillO
Here is a good video on this subject:
https://www.youtube.com/watch?v=STCGzanAyR0
Gets into a lot of detail we may not need in the 6502 world, but better stuff to have in your brain than the latest episode of The Gilmore Girls. Is that still a thing? I remember getting kicked out of the TV room so my better half and our daughter could watch that show.