6502.org

Posted: **Sun Dec 02, 2018 4:18 pm**

Yes, I'm letting the fitter set the pin assignments. I know from past experience with the Xilinx chips to let the fitter do that initially. Then its possible to adjust them in small increments if desired.

My state machine clock was the source of the errors. It was also defined towards the bottom of the source. I ended up defining the clock logic as a node and then reference the node as the clock source and that seemed to work better. I'm not sure why that was needed because clock sources can be derived from a product term.

Anyway, I'm happy that the source compiles now and am verifying all the logic has been properly translated.

Thanks all for your support.

Daryl

Posted: **Wed Dec 05, 2018 7:37 pm**

I have gone over the fitter report and I believe all is behaving as it should.

My next step will be to get an actual ATF1504 programmed and tested. That may take some time as my free time is very limited these days.

I am posting the source and fitter file for those who may want to give it a try, or at least look it over.

Thanks!

Daryl

Posted: **Tue Mar 12, 2019 2:10 am**

Forgive me, I am apparently being dense, but I am having trouble understanding the relationship between

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CS1

and

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/CS2

.

I am working on a W65C265 project, I have done a few in the past, but this time I need SPI support. I have programmed a XC9572XL to be a 65SPI. The interface makes sense, except for what to do with

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CS1

and

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/CS2

.

I am using CS1B on the '265 to map the the 65SPI into the address range of (00)DFC0-(00)DFFF, but are

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CS1

and

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/CS2

mirrors of each other, or do I pick which I want to use, or is it something completely else.

I can't find any schematics that show its use that have those pins named in the schematic.

As I say, I am sure I am just being dense, but could anyone clarify this for me?

Posted: **Tue Mar 12, 2019 2:18 am**

Having two chip selects often makes address decoding simpler and potentially faster (with fewer cascaded gates), and having one be positive logic and one be negative logic often helps too. This is common with 65xx I/O ICs. Take advantage and use them both.

Posted: **Tue Mar 12, 2019 3:14 am**

jockm wrote:

do I pick which I want to use, or is it something completely else.

The device is selected only when CS1 is high and /CS2 is low. All other combinations cause it to be de-selected.

In a simple scenario you might choose not to use CS1 (permanently tying it high instead), and drive /CS2 from a suitable address decoder. Or, you might tie /CS2 low, and drive CS1 from a suitable decoder. In other scenarios you might wish to actively use both, as Garth suggests.

-- Jeff

ps- welcome, jockm !

Posted: **Tue Mar 12, 2019 4:27 am**

There's a table at the bottom of page 2 in the manual titled "Register Address Map" showing the CS relationship. As Garth said, many 65xx IO chips used that configuration so I implemented on my design as well.

Daryl

Posted: **Tue Mar 12, 2019 4:52 am**

Dr Jefyll wrote:

jockm wrote:

do I pick which I want to use, or is it something completely else.

The device is selected only when CS1 is high and /CS2 is low. All other combinations cause it to be de-selected.

Awesome, thank you. Everything has clicked into place now

Posted: **Tue Mar 12, 2019 4:54 am**

8BIT wrote:

I have gone over the fitter report and I believe all is behaving as it should.

My next step will be to get an actual ATF1504 programmed and tested. That may take some time as my free time is very limited these days.

I am posting the source and fitter file for those who may want to give it a try, or at least look it over.

Thanks!

Daryl

I confess I have not had any time to work on this more. I see the files have been downloaded over 60 times. Has anyone tried it out on an ATF1504?

I'd be interested in any feedback.

thanks!

Daryl

Posted: **Tue Mar 12, 2019 4:54 am**

8BIT wrote:

There's a table at the bottom of page 2 in the manual titled "Register Address Map" showing the CS relationship. As Garth said, many 65xx IO chips used that configuration so I implemented on my design as well.

Yeah for whatever reason I just wasn't seeing it. Brain got hung up on the slightly different naming (/ vs B) for no good reason and I couldn't see past it. The fog has lifted

Posted: **Tue Mar 12, 2019 4:59 am**

jockm wrote:

Yeah for whatever reason I just wasn't seeing it. Brain got hung up on the slightly different naming (/ vs B) for no good reason and I couldn't see past it. The fog has lifted

Glad to hear it - we've all been there

Daryl

Posted: **Tue Mar 12, 2019 8:12 am**

jockm wrote:

Awesome, thank you. Everything has clicked into place now

Welcome to the forum, jockm!

Quote:

I am working on a W65C265 project

Feel free to start a thread about your project and your progress! Or just drop in when you have a question or a major triumph. Or introduce yourself.

Posted: **Thu Aug 08, 2019 8:03 am**

Hi Daryl,

I downloaded the PLD and was puzzled about the error message

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---------------------------------------------------------
 Fitter_Pass 1, Preassign = KEEP, LOGIC_DOUBLING : OFF 
 ... 
## ERROR : Bad user pin assignement : 68
 ## ERROR : Bad user pin assignement 
---------------------------------------------------------

When I checked the file I found that you are using the "NODE" as opposed to the "PINNODE" statement for burried cells. After replacing them it now compiles without
error messages

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PINNODE   = [si0..7];			/* shift in data reg */
PINNODE   = [so0..7];			/* shift out data reg */
PINNODE   = [st0..4];			/* SPI state counter */
PINNODE   = TMO;				/* SPI Enable reg */
PINNODE   = IER;				/* int enable reg */
PINNODE   = BSY;				/* busy flag reg */
PINNODE   = CPOL;				/* Clock polarity reg */
PINNODE   = CPHA;				/* Clock Phase reg */
PINNODE   = INT;				/* FIN/INT register */
PINNODE   = ECE;				/* Ext Clk Enable */
PINNODE   = CKSEL;				/* Int/EXT Clk sel */
PINNODE   = RMODE;				/* Read only Mode */
PINNODE   = STCLK;				/* State machine clock */

I'm planning to integrate it into one of my 6502SBCs, but not too soon as I'm still very busy with other projects (I'm looking for a SPI interface for my PDP-11, which is the reason I took a look at your code)

In any case thanks a lot for sharing and migrating your code to the still available 5-volts CPLD.

Peter

Posted: **Thu Aug 08, 2019 11:41 am**

Hi Peter,

Thanks for the recommendation. I'll give that change a try.

As far as I know, you will be the first to put this code to test. I never got around to buying parts to test it. I'll be interested in hearing your progress.

Thanks!

Daryl

Posted: **Fri Jan 24, 2020 6:20 pm**

Would it be possible to use the original 65SPI and use the newer one later when it's been perfected? I mean from a programming perspective. I have a project that needs SPI, and this is the only reasonable method of getting it.

Posted: **Fri Jan 24, 2020 10:18 pm**

The 65SPI was originally implemented on a no-longer-produced CPLD. It's not really possible to do that.
The new one is just the old one that's been adapted, and it's probably already fine. As I understand it, it's just that nobody has tested it in a currently-available CPLD like the ATF1504.

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