1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

ElEctric_EyE · Post by **ElEctric_EyE** » Wed Sep 17, 2014 11:26 pm

Garth, 2 questions quickly come to mind regarding this new path I'm taking on this 6-layer board using the Cadsoft Eagle program for PCB design. I'm researching them, but you may already know:
1) Can one use the Eagle program for PCB development without the schematic entry first? My initial experience seems like it wants a schematic first.
2) Since I aim for 6 layers and 2 power planes, should I have slower signals on the top and bottom planes? Then the Power and Ground planes, then finally sandwiched in the middle planes are the higher speed signals which would provide a natural bypass capacitance using FR4 material?

GARTHWILSON · Post by **GARTHWILSON** » Thu Sep 18, 2014 5:45 am

EE, I'm not familiar with Eagle, but I'm sure you don't need to use the schematic capture if you don't want to. My CAD (Easy PC Pro) has schematic capture but I don't like the way any of the schematic captures I've tried work, so I still do my schematics by hand; but in the CAD, I can still pick the devices out of the libraries I built and put the parts on a board and connect them up the way I want, without using the ratsnesting and such. Even though the CAD came with libraries with lots of parts pre-made, I've made my own for denser layouts. But regardless, there will always be various parts that won't come in any CAD's pre-made libraries, so you need to be able to make those parts. Recent examples for me have included a chip antenna, feedthru capacitor, balun, various inductors, and chip crystals.

Normally the order of the layers in a 6-layer board is approximately what you mention:

signal 1 generally going at 0°
power (bypassed to ground at all Vcc pins and anywhere a trace goes through a via from layer 1 to layer 6 if the signals are fast enough to matter since otherwise the return current cannot keep following the signal trace)
signal 2 generally going 45°
signal layer 3 generally going 135°
ground
and signal layer 4 generally going 90°.

Which signal layers are 0, 45, 90, and 135° is not really important except that it's good to have the 2nd and 3rd signal layers at 90° to each other to reduce inter-layer coupling, since they're next to each other. Having signal layers generally going the directions shown above will greatly reduce the number of vias you need.

Trying to keep the fastest signals on the inside may make it harder to route a dense board, and is not necessary anyway because if the power and ground layers are used correctly, you already have transmission lines that will keep from radiating or picking up noise even if they're on the outside. Just route a signal on the layer that goes the general direction that signal needs to go. When I worked in VHF/UHF power transistor applications engineering in the mid-1980's and was often building up power amplifiers for engineering testing of our parts under the conditions requested by the clients, we always used microstrip or coplanar waveguide, not stripline. In microstrip, the transmission line is always on the top, yet there's no radiation from it. In stripline, the signal lines are sandwiched between ground layers (and one could be a power plane bypassed to ground at places that are appropriate for the signal line).

ElEctric_EyE · Post by **ElEctric_EyE** » Wed Sep 24, 2014 12:38 am

Great information as always Garth. Many thanks for trying to help me!

I spent about 2 weeks trying to rise above the learning curve for Cadsoft Eagle and realized it was going to take up too much of the little time I have left to spare for this new chapter of the PVB project.

I've decided to stick with the PCB routing software I already know from Express PCB as I can route 90% of all the available signals off of the FPGA necessary with about 30 extra I/O pins left over using their ProtoPro service which limits the total board design to 21 square inches. 4 boards for $205US. The new boards will be 6"x3.5" vs the these current 3.8"x2.5" PVBs. The new boards will now have some new features, the most important being 2x 2Mx18 SyncRAMs for sprite generation or page flipping.

The following code and associated videos will show the speed of the 75 MHz 65Org16 working in unison with 8 functions of my 75MHz hardware graphics accelerator written in Verilog. The SyncRAM and Arlet's Hsync/VSync/pixel clock generator are running @150MHz. Thanks to Arlet way back, I have hsync and vsync signals from the SYNC generator going to the 65Org16 cpu through an expanded 16-bit status flag register, and also branch testing opcodes for branch on clear or set for the added status flag bits. I have yet to post this version of 65Org16 on Github.

The hardware accelerator uses the RDY flag in order to halt the cpu so the accelerator can do it's work on the videoRAM. However, there is still video interference when the software chooses not to plot without regarding the state of hvsync or vsync and so video interference results.

Since I am going to have to cannibalize the memory IC's from 4 out of the 5 boards, I thought that the best way to close this thread would be to display some basic functions, especially with different delay variables.

Each post will include the 65Org16 coding and the video. This is more for me than anyone else and I thank 6502.org for tolerating my indulgence, but hopefully some may find it interesting and inspirational since I started designing the first version of these boards back in Aug 6, 2012. I did it in order to learn the discipline of the Verilog language. I'm a slow learner, but hardware design goes in tandem with HDL, so the design must change for the little I now know.

Here are the 8 functions of the current 2D hardware accelerator:

Code: Select all

8/26/2014 smg    Programming the 16-bit 2D Graphics 'LineGen' Accelerator
                
FUNCTION...............VARIABLE = 'description'....................R(ead)/W(rite)
________________________________________________________________________________
   
Line Generator............color = pixel color..........................RW
                            lx0 = X position start.....................RW
                            ly0 = Y position start.....................RW
                            lx1 = X position end.......................RW
                            ly1 = Y position end(*)....................RW
                      
Rectangle Fill............color = pixel color..........................RW
                          fXlen = Horizontal length....................RW
                          fYlen = Vertical length......................RW
                            fXs = X position start.....................RW
                            fYs = Y position start(*)..................RW
                      
Pixel Plot................color = pixel color..........................RW
                             Xp = X position...........................RW
                             Yp = Y position(*)........................RW

Read Pixel Color.............Xr = X position...........................RW
                             Yr = Y position(*)........................RW
                      colordata = 5-6-5 16bit R-G-B color data.........R
                                              
Copy & Paste Rectangle....bXlen = Horizontal length....................RW
                          bYlen = Vertical length......................RW
                            bXc = X position start of copy.............RW
                            bYc = Y position start of copy.............RW
                            bXp = X position start of paste............RW
                            bYp = Y position start of paste(*).........RW
                        
Character Plot............color = pixel color..........................RW
                         bcolor = background pixel color...............RW
                            Att = ASCII character + font...............RW
                             (0000000axxxxxxxx. xxxxxxxx = 8bit ASCII) 
                             (a = 1 C64, a = 0 DOS. FONTS) 
                             cX = X position...........................RW
                             cY = Y position(*)........................RW
                        
SIN LUT Generator........Xblock = (0..15) BRAM LUTs for X coordinates..RW
                         Yblock = (0..15) BRAM LUTs for Y coordinates..RW
                        Xoffset = placement within 1920 Horizontal.....RW
                        Yoffset = placement within 1080 Vertical.......RW
                          xfreq = # of SIN repetition within LUT1......RW
                          yfreq = # of SIN repetition within LUT2......RW
                         Xphase = (0..1023) Phase input to LUT1........RW
                         Yphase = (0..1023) Phase input to LUT2(*).....RW
                        
Square Root Generator........Xs = 16bit number.........................RW
                             Ys = 16bit number(*)......................RW
                           Root = SQRT(Xs^2 + Ys^2)....................R
________________________________________________________________________________
NOTES:
(*) This Verilog Hardware Function is initiated after a write to these registers.

Also, bear with me as it take longer to process video through youtube so the software will most likely be posted first.

ElEctric_EyE · Post by **ElEctric_EyE** » Wed Sep 24, 2014 1:23 am

This is software to init the 64Kx16 ZeroPage & 64Kx16 StackPage pointers within the 65Org16 (only 1Kx16 used for each utilizing FPGA BRAMs). This is because early on I allowed the cpu to directly access the videoRAM for things like plotting characters through software and screen clearing. That is before I understood how to make Verilog perform these functions in HDL... The videoRAM started at $00000000. This is no longer allowed, the accelerator now performs all the plotting, so this is legacy code (I just now realize

). Also this code initializes the H/V Sync Generator timings and then clears the videoRAM using the Rectangle Fill with color #%0000000000000000 (black):

Code: Select all

BEGIN:            LDA #$1000              
                  TAZP                    ;SET ZEROPAGE @$1000_0000
                  LDA #$1001
				      TASP                    ;SET STACKPAGE @$1001_0000                  
                                                                                                                   
                  LDA #1920               ;2430 (2200 ideal for 67.5kHz) total H cycles      @148.5MHz 16.363uS ->  61.111kHz          
                  STA hVIDEO                                                                        
                  LDA #205                 ;205                                                      
                  STA hFRONT                                                                        
                  LDA #50                  ;50                                                    
                  STA hSYNC                                                                        
                  LDA #255                 ;255                                                     
                  STA hBACK
                  
                  LDA #1080                ;1139 total     @148.5MHz ->  1139 x 16.363uS = 18.638mS = 53.654Hz
                  STA vVIDEO                                                                               
                  LDA #2                   ;2                                                              
                  STA vFRONT                                                                                
                  LDA #55                  ;55                                                            
                  STA vSYNC                                                                                 
                  LDA #2                   ;2                                                             
                  STA vBACK                                                                                                              
                  
rock              LDA #%0000000000000000                  ;16-bit 565 RGB               
                  STA color
                  
                  LDA #1919 
                  STA fXlen
                  LDA #1079
                  STA fYlen
                  LDA #0
                  STA fXs
                  STA fYs                  ;FILL!

ElEctric_EyE · Post by **ElEctric_EyE** » Wed Sep 24, 2014 1:39 am

Continuing, this final part of this software draws lines from the center of the screen to the outer edges with a significant delay. The variable 'color' is derived from a pseudo-random HDL number generator. It's not so random as every number is the same upon power-up but it does the job OK. Next board will have a true random number generator built in hardware.

Code: Select all

BEGIN:            LDA #$1000              
                  TAZP                    ;SET ZEROPAGE @$1000_0000
                  LDA #$1001
				      TASP                    ;SET STACKPAGE @$1001_0000                  
                                                                                                                                       
                  LDA #1920               ;2430 (2200 ideal for 67.5kHz) total H cycles      @148.5MHz 16.363uS ->  61.111kHz          
                  STA hVIDEO                                                                        
                  LDA #205                 ;205                                                      
                  STA hFRONT                                                                        
                  LDA #50                  ;50                                                    
                  STA hSYNC                                                                        
                  LDA #255                 ;255                                                     
                  STA hBACK
                  
                  LDA #1080                ;1139 total     @148.5MHz ->  1139 x 16.363uS = 18.638mS = 53.654Hz
                  STA vVIDEO                                                                               
                  LDA #2                   ;2                                                              
                  STA vFRONT                                                                                
                  LDA #55                  ;55                                                            
                  STA vSYNC                                                                                 
                  LDA #2                   ;2                                                             
                  STA vBACK                                                                                                              
                  
rock              LDA #%0000000000000000                  ;16-bit 565 RGB               
                  STA color
                  
                  LDA #1919 
                  STA fXlen
                  LDA #1079
                  STA fYlen
                  LDA #0
                  STA fXs
                  STA fYs                  ;FILL!

                  LDA rng
                  STA color
                  
                  LDX #0
                  LDA #1920/2
                  STA lx0
                  LDA #1080/2
                  STA ly0
liner1            TXA
                  STA lx1
                  JSR DELAY2
                  LDA #0
                  STA ly1
                  INX
                  CPX #1919
                  BNE liner1
                  
                  LDX #0
                  LDA #1920/2
                  STA lx0
                  LDA #1080/2
                  STA ly0
liner2            TXA
                  STA lx1
                  JSR DELAY2
                  LDA #1080
                  STA ly1
                  INX
                  CPX #1919
                  BNE liner2
                  
                  LDY #0
                  LDA #1920/2
                  STA lx0
                  LDA #1080/2
                  STA ly0
                  LDA #0
                  STA lx1
liner3            TYA
                  STA ly1
                  JSR DELAY2
                  INY
                  CPY #1080
                  BNE liner3
                  
                  LDY #0
                  LDA #1920/2
                  STA lx0
                  LDA #1080/2
                  STA ly0
                  LDA #1919
                  STA lx1
liner4            TYA
                  STA ly1
                  JSR DELAY2
                  INY
                  CPY #1080
                  BNE liner4

                  JMP rock

Here is the DELAY2 routine:

Code: Select all

DELAY2            PHY
                  PHX
                  LDY #$0FFF
GHJ               DEY
                  BNE GHJ
                  PLX
                  PLY
                  RTS

Quite a few cycles! I'll ry to make the video tonight.

ElEctric_EyE · Post by **ElEctric_EyE** » Wed Sep 24, 2014 2:24 am

This video is with the delay.
This video is without delay.

BigEd · Post by **BigEd** » Wed Sep 24, 2014 5:45 am

Thanks EEye for taking us on this journey with you! It's easy enough for two years to pass without any visible progress, so congratulations for showing the determination to bring this design to a demo-worthy state and posting about your problems and progress. I'm sure you feel satisfied that you've learnt a huge amount by battling through this far: we don't often cast ourselves back to the beginning of a project and consider what used to be mysterious to us, or what we felt to be beyond our understanding.

Cheers
Ed

BigDumbDinosaur · Post by **BigDumbDinosaur** » Wed Sep 24, 2014 3:33 pm

BigEd wrote:

Thanks EEye for taking us on this journey with you!

I've been reading about this project as well as it progressed. As Ed noted, it's easy to lose sight of the early days when success of any kind seemed uncertain and some problems seemed insurmountable. You've come a long ways with it.

ElEctric_EyE · Post by **ElEctric_EyE** » Wed Sep 24, 2014 11:08 pm

Guys, thanks for your thoughts!

BigEd wrote:

Thanks EEye for taking us on this journey with you! It's easy enough for two years to pass without any visible progress, so congratulations for showing the determination to bring this design to a demo-worthy state and posting about your problems and progress...

The help I've received early on, from it seems, the most knowledgeable folk has really inspired me to continue to as far as I have progressed. If they would have said "no, that won't work" well then I probably would have believed them. But I was told the parallel video board idea would work and so I made it work even though sometimes troubleshooting was very laborious. In fact, I think I would've never even considered the project, nor even posted the idea, if I was expecting my 'ignorant' questions not to be answered.

BigEd wrote:

... I'm sure you feel satisfied that you've learnt a huge amount by battling through this far: we don't often cast ourselves back to the beginning of a project and consider what used to be mysterious to us, or what we felt to be beyond our understanding...

Looking back, the very first thing that worked in my initial Verilog coding, was reading the Synchronous RAM consistently and sending the data to the videoDAC. I think the resolution was 640x480 with a pixel clock of 25MHz (The core was capable of running 4x that speed soon afterwards). That got the wheels turning and the motivation was high., but...

Recently from my point of view, things have stagnated abit these past couple of weeks. I realized something had to change. I was making no progress, so a new board design will have to flex some more mental muscle, but my brain needs a rest from the disciplines of Verilog and PCB construction! This is the problem with a one man team.

Time for some more fun stuff with software for the next week or 2...

ElEctric_EyE · Post by **ElEctric_EyE** » Thu Sep 25, 2014 12:30 am

The next idea was supposed to be simple but I think it shows a flaw somewhere in modification of the rng generator. It plots 65536 random pixels, random X, random Y and random color...Not spending too much time on this. There's a bit of a problem on the 1024 border vertical and horizontal, there seems to be a concentration of pixels, also too many zero values. Oh well, F it, I'm on to the next one. Pseudo Random Number Generators in HDL are not suited for the purpose I had envisioned.
1)read the rng, put a value in the color variable.
2)read the rng, put the value in X position register
3)read the rng, put the value in Y position register and autoplot.

Code: Select all

LDA #1920               ;2430 (2200 ideal for 67.5kHz) total H cycles      @148.5MHz 16.363uS ->  61.111kHz          
                  STA hVIDEO                                                                        
                  LDA #205                 ;205                                                      
                  STA hFRONT                                                                        
                  LDA #50                  ;50                                                    
                  STA hSYNC                                                                        
                  LDA #255                 ;255                                                     
                  STA hBACK
                  
                  LDA #1080                ;1139 total     @148.5MHz ->  1139 x 16.363uS = 18.638mS = 53.654Hz
                  STA vVIDEO                                                                               
                  LDA #2                   ;2                                                              
                  STA vFRONT                                                                                
                  LDA #55                  ;55                                                            
                  STA vSYNC                                                                                 
                  LDA #2                   ;2                                                             
                  STA vBACK                                                                                                              
                  
                  LDA #%0000000000000000                  ;16-bit 565 RGB               
                  STA color
                  
                  LDA #1919 
                  STA fXlen
                  LDA #1079
                  STA fYlen
                  LDA #0
                  STA fXs
                  STA fYs                  ;FILL!

                  LDX #$FFFF
rock              LDA rng
                  STA color
                  
                  LDA rng
                  STA Xp
                  LDA rng
                  STA Yp

                  DEX
                  BNE rock
                  
im                JMP im

The current rng generator:(I have modified the original code which is shown below. All credits remain, so one can search out the original code from the original authors)

Code: Select all

//------------------------------------------------------------------------------
//    File Name:  PRBS_ANY.v
//      Version:  1.0 
//         Date:  6-jul-10
//------------------------------------------------------------------------------
//
//      Company:  Xilinx, Inc.
//  Contributor:  Daniele Riccardi, Paolo Novellini
// 
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2010 Xilinx, Inc.
//                All rights reserved.
//
//--------------------------------------------------------------------------
// DESCRIPTION
//--------------------------------------------------------------------------
//   This module generates or check a PRBS pattern. The following table shows how  
//   to set the PARAMETERS for compliance to ITU-T Recommendation O.150 Section 5.
//    
//   When the CHK_MODE is "false", it uses a  LFSR strucure to generate the
//   PRBS pattern.
//   When the CHK_MODE is "true", the incoming data are loaded into prbs registers
//   and compared with the locally generated PRBS 
// 
//--------------------------------------------------------------------------
// PARAMETERS 
//--------------------------------------------------------------------------
//   CHK_MODE     : true =>  check mode
//                  false => generate mode
//   INV_PATTERN  : true : invert prbs pattern
//                     in "generate mode" the generated prbs is inverted bit-wise at outputs
//                     in "check mode" the input data are inverted before processing
//   POLY_LENGHT  : length of the polynomial (= number of shift register stages)
//   POLY_TAP     : intermediate stage that is xor-ed with the last stage to generate to next prbs bit 
//   NBITS        : bus size of DATA_IN and DATA_OUT
//
//--------------------------------------------------------------------------
// NOTES
//--------------------------------------------------------------------------
//
//
//   Set paramaters to the following values for a ITU-T compliant PRBS
//------------------------------------------------------------------------------
// POLY_LENGHT POLY_TAP INV_PATTERN  || nbr of   bit seq.   max 0      feedback   
//                                   || stages    length  sequence      stages  
//------------------------------------------------------------------------------ 
//     7          6       false      ||    7         127      6 ni        6, 7   (*)
//     9          5       false      ||    9         511      8 ni        5, 9   
//    11          9       false      ||   11        2047     10 ni        9,11   
//    15         14       true       ||   15       32767     15 i        14,15   
//    20          3       false      ||   20     1048575     19 ni        3,20   
//    23         18       true       ||   23     8388607     23 i        18,23   
//    29         27       true       ||   29   536870911     29 i        27,29   
//    31         28       true       ||   31  2147483647     31 i        28,31   
//
// i=inverted, ni= non-inverted
// (*) non standard
//----------------------------------------------------------------------------
//
// In the generated parallel PRBS, LSB is the first generated bit, for example
//         if the PRBS serial stream is : 000001111011... then
//         the generated PRBS with a parallelism of 3 bit becomes:
//            data_out(2) = 0  1  1  1 ... 
//            data_out(1) = 0  0  1  1 ...  
//            data_out(0) = 0  0  1  0 ... 
// In the received parallel PRBS, LSB is oldest bit received
//
// RESET pin is not needed for power-on reset : all registers are properly inizialized 
// in the source code.
// 
//------------------------------------------------------------------------------
// PINS DESCRIPTION 
//------------------------------------------------------------------------------
//
//      RST          : in : syncronous reset active high
//      CLK          : in : system clock
//      DATA_IN      : in : inject error (in generate mode)
//                          data to be checked (in check mode)
//      EN           : in : enable/pause pattern generation/check
//      DATA_OUT     : out: generated prbs pattern (in generate mode)
//                          error found (in check mode)
//
//-------------------------------------------------------------------------------------------------
// History:
//      Version    : 1.0
//      Date       : 6-jul-10
//      Author     : Daniele Riccardi
//      Description: First release
//-------------------------------------------------------------------------------------------------
// no timescale needed

module PRBS_ANY(RST, CLK, EN, DATA_OUT );

  //--------------------------------------------		
  // Configuration parameters
  //--------------------------------------------		
   parameter CHK_MODE = 0;
   parameter INV_PATTERN = 0;
   parameter POLY_LENGHT = 31;
   parameter POLY_TAP = 3;
   parameter NBITS = 16;

  //--------------------------------------------		
  // Input/Outputs
  //--------------------------------------------		

   input RST;
   input CLK;
   input EN;
   output reg [NBITS - 1:0] DATA_OUT = {NBITS{1'b1}};;

  //--------------------------------------------		
  // Internal variables
  //--------------------------------------------		

   wire [1:POLY_LENGHT] prbs[NBITS:0];
   wire [NBITS - 1:0] data_in_i;
   wire [NBITS - 1:0] prbs_xor_a;
   wire [NBITS - 1:0] prbs_xor_b;
   wire [NBITS:1] prbs_msb;
   reg  [1:POLY_LENGHT]prbs_reg = {(POLY_LENGHT){1'b1}};
	reg  [NBITS - 1:0] DATA_IN;

  //--------------------------------------------		
  // Implementation
  //--------------------------------------------		

   assign data_in_i = INV_PATTERN == 0 ? DATA_IN : ( ~DATA_IN);
   assign prbs[0] = prbs_reg; 
   
   genvar I;
   generate for (I=0; I<NBITS; I=I+1) begin : g1
      assign prbs_xor_a[I] = prbs[I][POLY_TAP] ^ prbs[I][POLY_LENGHT];
      assign prbs_xor_b[I] = prbs_xor_a[I] ^ data_in_i[I];
      assign prbs_msb[I+1] = CHK_MODE == 0 ? prbs_xor_a[I]  :  data_in_i[I];  
      assign prbs[I+1] = {prbs_msb[I+1] , prbs[I][1:POLY_LENGHT-1]};
   end
   endgenerate

   always @(posedge CLK) begin
      if (RST) begin
         DATA_OUT <= {NBITS{1'b1}};
         prbs_reg <= {POLY_LENGHT{1'b1}};
			DATA_IN <= DATA_OUT;
      end
      else if(EN) begin
         DATA_OUT <= prbs_xor_b;
         prbs_reg <= prbs[NBITS];
			DATA_IN <= DATA_OUT;
      end
			else begin
				DATA_OUT <= 16'h0000;
				prbs_reg <= prbs[NBITS];
				DATA_IN <= DATA_OUT;
			end
  end

endmodule

ElEctric_EyE · Post by **ElEctric_EyE** » Fri Sep 26, 2014 8:57 pm

There is something seriously wrong with the HDL rng.

I did modify the Verilog awhile ago and it seemed to be OK for most uses, but I may have done a modification incorrectly.

Now when I utilize it for a random sample for an X coordinate, then mask the value for 1920 (AND #1919) and then another sample for a Y coordinate and mask that value for 1080 (AND #1079) I see something strange. I will post a pic before further experimentation with the rng generator code. In real-time, all random colored dots are being placed within the rectabgles as seen in the pic.

In the modified software code below (from the one above) for the random PLOT, there is the BCF0C $FFFE. BCF0C stands for Branch if Control Flag 0 is clear (i.e. zero). This branch opcode is in a constant loop testing the hsync signal as it has been wired to this control flag 0 bit in the status register of the 65Org16 cpu in the top_level design. As soon as it goes high, the cpu sends the final command to the LineGen accelerator for it to perform a single cycle plot, well within the time of an inactive hsync pulse, I'm not sure how many cycle it is though. The hardware accelerator then puts the cpu in a RDY state until the hardware accelerator is done. This results in a no address conflict between the VGA controller and the hardware accelerator, otherwise the result would be the snow effect.

Code: Select all

rock              LDA rng
                  STA color
                  
                  LDA rng
                  AND #1919
                  STA Xp
                  LDA rng
                  AND #1079
                  
                  BCF0C $FFFFE            ;Branch if Control Flag 0 is Clear (0). CF0 is HSYNC input, so branch to itself and wait until hsync = 1, a non display period
                  
                  STA Yp                  ;PLOT! (single cycle).
                  
imp               JMP rock

MichaelM · Post by **MichaelM** » Fri Sep 26, 2014 10:08 pm

EEyE:

I don't think that there is something seriously wrong with the RNG. Instead, I am thinking that the equation you are using for the modulus operation, i.e. AND #1919 and/or AND #1079, is the issue.

Using the AND #xxxxx instruction to perform a modulus operation which is intended to restrict a pseudo-random value to a particular range only works if the desired range is a power of 2. Neither the 1920 nor the 1080 ranges to which you wish to restrict your RNG samples are powers of two.

Expanding these two numbers into the binary equivalents will show you why the values are falling into little rectangles: 1919 => 111_0111_1111, and 1079 => 100_0011_0111. Those zeroes in the masks are not at all desirable.

You could try masking it with 111_1111_1111 and then checking if the number exceeds 1919 or 1079, and if does, get another sample.

ElEctric_EyE · Post by **ElEctric_EyE** » Fri Sep 26, 2014 11:14 pm

MichaelM wrote:

...You could try masking it with 111_1111_1111 and then checking if the number exceeds 1919 or 1079, and if does, get another sample.

Ah Michael, thanks very much!
Absolutely right. I had forgotten. There must be a mental block in there somewhere in my brain.
I've mod'd the software and it looks like this and is working almost 100%, but I've not yet added the part that checks if the number exceeds the borders...

Code: Select all

...
rock              LDA rng
                  STA color
                  
                  LDA rng
                  AND #%0000011111111111
                  STA Xp
                  LDA rng
                  AND #%0000011111111111
                  
                  BCF0C $FFFFE            ;Branch if Control Flag 0 is Clear (0). CF0 is HSYNC input, so branch to itself and wait until hsync = 1, a non display period
                  
                  STA Yp                  ;PLOT! (single cycle)
                  
imp               JMP rock

ElEctric_EyE · Post by **ElEctric_EyE** » Sat Sep 27, 2014 10:16 pm

I needed a refresh on my 6502 software, it has been awhile! Sorry about that and thanks for the help. I took Michael's suggestion and the following software works. I will have 2 videos for this speed comparison. One using the software below, where it waits for hsync retrace to plot with no 'snow effect'. The other video will use the same software but with the 'BCFOC $FFFE' line commented out, so the hardware accelerator will plot AFAP but with the 'snow effect'. The speed difference is dramatic and I aim for the higher plotting speeds being shown in these videos, without the 'snow effect', in the next build of these video boards.

Code: Select all

                  
rock              LDA rng
                  STA color
                  
NG                LDA rng                  ;get 16-bit sample from HDL pseudo random number generator
                  AND #%0000011111111111
                  CMP #1919
                  BCS NG                   ;if random sample is >1919 get another random sample
                  STA Xp
NG1               LDA rng
                  AND #%0000011111111111
                  CMP #1079
                  BCS NG1                 ;if random sample is >1079 get another sample
                  
                  BCF0C $FFFFE            ;Branch if Control Flag 0 is Clear (0). CF0 is HSYNC input, so branch to itself and wait until hsync = 1, a non display period
                  
                  STA Yp                  ;PLOT! (single cycle)
                  
imp               JMP rock

ElEctric_EyE · Post by **ElEctric_EyE** » Sun Sep 28, 2014 6:19 pm

Hit a delay. Had to backup files, reinstall OS and troubleshoot slow internet speeds. The videos are blurry, I'll have to try to fix this...
The pixel plot without delay is difficult to see what's going on since this function takes a single cycle, it creates alot of interference.
The second video is easier to see what's going on and shows artifacts from the PRNG.
Pixel Plot function with no delay.
Pixel Plot function waiting for hsync.

1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board

Re: 1080p HD Video on custom FPGA/VDAC/2MBx18 SyncRAM board