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module SRAMif( input clk,
input vramCS, //cpu is reading/writing to videoRAM
input cpuWE,
input RAMWE, //LineGen is drawing
inout [15:0] SRD,
input [15:0] BACCout, //pixel color from cpu
input [9:0] X, //LSB of LineGen address
input [8:0] Y, //MSB
input [20:0] Vaddr, //pixel clock address from HVSync Generator
input [31:0] cpuAB,
output reg [20:0] SRaddr,
//output reg [15:0] SRDO, //to cpu
output reg SRWEn
);
reg SRWEn2;
reg [15:0] SRDO;
always @(posedge clk) begin
SRWEn2 <= SRWEn;
SRaddr <= RAMWE ? {2'b00, Y, X} : vramCS ? cpuABopt : Vaddr;
SRWEn <= !(RAMWE || (vramCS && cpuWE));
if (SRWEn)
SRDO <= BACCout;
end
reg [20:0] cpuABopt;
always @* begin //optimize the videoRAM address for plotting (X,Y) in the (LSB,MSB) for indirect indexed
cpuABopt [20:19] <= 2'b00; //bank bits
cpuABopt [18:10] <= cpuAB [24:16]; //Y[8:0]
cpuABopt [9:0] <= cpuAB [9:0]; //X[9:0]
end
assign SRD = SRWEn2 ? 16'hZZZZ : SRDO; //I/O MUX'd latch to SyncRAM databus. High 'Z' during a read
endmoduleCode: Select all
BCF0C $FFFE ;CF = LineGen Ready. 1 = ready
Code: Select all
PLOT:
begin
RAMWE <= 1;
X <= x0 >> 3;
Y <= y0 >> 3;
end