Page 4 of 4
Re: Issues with 6502?
Posted: Sat Aug 02, 2025 4:20 pm
by Michael
Would there be any advantage driving the VIA active-high chip select inputs directly with the A12 and A13 lines, besides eliminating some gates and propagation delay in the decoding circuitry? VIA-1 would be addressed at $5000..$500F while VIA-2 would be addressed at $6000..$600F.
Re: Issues with 6502?
Posted: Sat Aug 02, 2025 8:56 pm
by Niek6502
Would there be any advantage driving the VIA active-high chip select inputs directly with the A12 and A13 lines, besides eliminating some gates and propagation delay in the decoding circuitry? VIA-1 would be addressed at $5000..$500F while VIA-2 would be addressed at $6000..$600F.
The current glue I use consumes these addresses:
Code: Select all
0000-3FFF : SRAM
6000-6FFF : VIA-1
7000-7FFF : VIA-2
8000-FFFF : EEPROM
It leaves a contiguous 4000-5FFF available for me for something else (not sure what yet). At some point I plan to replace the current glue with something "tighter", probably when I want to maximize RAM (like decrease ROM that then only loads programs from storage into RAM).
Hope that makes sense.
-Niek.
Re: Issues with 6502?
Posted: Mon Aug 25, 2025 3:58 am
by Michael
Makes perfect sense.
I just think it's kinda' neat that you can 'slot' a bunch of 6500 series peripherals into I/O space without additional address decoder logic. In my rendering of the "very basic whole-computer" diagram from the Potpourri chapter of "The Primer" I included a table of I/O slots available for 6500 series peripheral chips within the minimally decoded I/O block.
Have fun. Cheerful regards.
Re: Issues with 6502?
Posted: Sun Sep 21, 2025 9:31 pm
by J64C
Hi Mike. Nice clean diagram you have there.
With JW2 for the CPU select, you can just put in a 3.3K pulldown and you can swap and change the CPU without having to reconfigure the board.
Re: Issues with 6502?
Posted: Sun Sep 21, 2025 11:45 pm
by GARTHWILSON
Hi Mike. Nice clean diagram you have there.
With JW2 for the CPU select, you can just put in a 3.3K pulldown and you can swap and change the CPU without having to reconfigure the board.
The pin-1 Vss is not a signal input, but rather a ground connection. I imagine Bill Mensch labored over which pins of the DIP could be sacrificed to get the additional signal lines of the W65C02S, and probably didn't like the idea of eliminating that second ground connection, as it would make the rest of the circuit more vulnerable to problems from groundbounce, but perhaps felt he had no choice. A ground connection should have the lowest impedance possible, and a 3.3K won't give any value as a ground connection for the non-WDC part. And for the WDC part, since the VPB output is usually high, a 3.3K pulldown would result in an extra 1.5mA of supply current, just wasted. I would stick with the jumper.
Re: Issues with 6502?
Posted: Mon Sep 22, 2025 2:32 am
by J64C
Ah my apologies, right you are. I was thinking of a different pin and didn't realise the circuit was for a generic 65C02.
I was on a totally different thought train and was thinking about W65C02 & W65C816 Interchangeability.
Re: Issues with 6502?
Posted: Mon Sep 22, 2025 7:41 pm
by BigDumbDinosaur
The pin-1 Vss is not a signal input, but rather a ground connection. I imagine Bill Mensch labored over which pins of the DIP could be sacrificed to get the additional signal lines of the W65C02S, and probably didn't like the idea of eliminating that second ground connection...
...ergo the PLCC44 package, which has two grounds (pins 1 and 23). Aside from that, the PLCC package offers improved density, so there are two good reasons to use it instead of the DIP40 version.