Kestrel 8K Finished!

For discussing the 65xx hardware itself or electronics projects.
Memblers
Posts: 64
Joined: 16 Jan 2003
Location: Indianapolis
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Post by Memblers »

That wasn't it, but those do look interesting.

Here's what it I was referring to, I just found it:
http://www.novatek.com.tw/english/produ ... d=0.301948
kc5tja
Posts: 1706
Joined: 04 Jan 2003

Kestrel Upload Tool is . . . uploaded.

Post by kc5tja »

I have updated the distribution on my website ( http://www.falvotech.com/projects/kestrel/8k.php ) to now include the Kestrel's upload tool. You can grab it using Darcs, or you can grab the .tar.gz file.

The upload tool is "Linux specific", but is easily modified for other OSes. I've factored the code mercilessly, so it should be easy to follow for anyone.

If anyone is willing to create a Windows port of the software, I'll be happy to include it in the distribution, but beware, I cannot test it.

I think my next step with the development of the Kestrel is the creation of a software-managed SPI interface with the host PC. Since the host PC represents an amalgamation of other utilities that I'd like to exploit from the Kestrel (e.g., a disk, mouse, keyboard, text- and/or graphical-display, network connection,e tc), I'm probably going to adapt some networking protocol over the SPI interface. I'm strongly considering ATM at the moment. However, I am also looking at time-division multiplexing as well (particularly effective since SPI is perfectly capable of full-duplex operation). A DTM-like system in particular looks rather trivial to implement, potentially even easier than ATM.

Traditional packet switching is also an option, but from what I've seen, software to support arbitrary length packets is more complex (and memory requirements aren't predictable). ATM and DTM involve fixed-length packets (called cells for ATM, and slots for DTM), which should make software development easier. DTM also promises less than 10% network overhead too, at least when fully utilized, while ATM imposes a fixed 10% network overhead. Traditional packet switching goes between 5% and 250%, depending on packet length.
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dclxvi
Posts: 362
Joined: 11 Mar 2004

Post by dclxvi »

GARTHWILSON wrote:
The official spec. says I²C's clock and data lines are supposed to remain high when inactive; but in my limited experience, it simply doesn't matter what these lines do between the time a "stop" condition is generated and when the next "start" condition is generated. Maybe the idea is that low-power devices can scavenge their power from these lines between low pulses, like 1-Wire.
The purpose of this is to allow more than one master to be connected to the bus simultaneously. For example, a 6502 with 6522 and a PC could be both be used as masters, with a 24C256 (32K * 8 bit) EEPROM and/or other slave devices. There's a procedure for arbitration when more than one master attempts to take control of an idle bus. It does not matter to a slave device which master has control of the bus, so a slave device does not need to care about the state of an idle bus, as you have found. One master seems to be a common configuration; I've never used more than one master on the bus.
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