Re: New WDC W65C268QBX Board
Posted: Fri Mar 31, 2017 10:16 pm
I verified the contents of the ROM against the listing. The part from Reset up to the baudrate detection seems to be identical.
The baudrate detection syncs to the lowspeed timer 1. The clock is 32768 Hz. When T1 reaches 0 the fast clock is used to DEX X from $1000. This is $1000 x 5 fast cycles. Then T1Clo is read and compared against two tables, one for maximum values, one for minimum values.
Now for verification:
($1000 x 5 / 1843200) x $8000 = $016C. As the counter decrements => $100-$6C = $94. The ROM tables have $92 as minimum and $97 as maximum.
($1000 x 5 / 2457600) x $8000 = $0111. As the counter decrements => $100-$11 = $EF. The ROM tables have $EE as minimum and $F2 as maximum.
($1000 x 5 / 3686400) x $8000 = $00B6. As the counter decrements => $100-$B6 = $4A. The ROM tables have $48 as minimum and $4D as maximum.
($1000 x 5 / 4915200) x $8000 = $0088. As the counter decrements => $100-$88 = $78. The ROM tables have $77 as minimum and $7B as maximum.
($1000 x 5 / 6144000) x $8000 = $006D. As the counter decrements => $100-$6D = $93. The ROM tables have $0A as minimum and $12 as maximum - WHICH ARE TOTALLY WRONG.
Contrary to my first verification the compare against the table values is successful for all frequencies but 6,144MHz. If the first comparision against max exits too early, the following compare against min correct this.
I have also verified that 4,9152MHz is running correctly - I did use 4,194304MHz erroneously. Mea culpa. I could also verify that 1,8432MHz works.
The upper frequency limit of my board seems to be 18,432MHz. At least using the crystal osc circuitry without further trimming. 20 and 22,1184MHz did oscillate but the program failed to work. This may also happen because the duty cycle of PHI2 was somewhere between 33/66 .. 40/60.
Next check will be program execution out of flash-eprom. The 39SF010 should arrive soon.
___
edit(1): T1L corrected to TIClo, added try with 1,8432MHz
The baudrate detection syncs to the lowspeed timer 1. The clock is 32768 Hz. When T1 reaches 0 the fast clock is used to DEX X from $1000. This is $1000 x 5 fast cycles. Then T1Clo is read and compared against two tables, one for maximum values, one for minimum values.
Now for verification:
($1000 x 5 / 1843200) x $8000 = $016C. As the counter decrements => $100-$6C = $94. The ROM tables have $92 as minimum and $97 as maximum.
($1000 x 5 / 2457600) x $8000 = $0111. As the counter decrements => $100-$11 = $EF. The ROM tables have $EE as minimum and $F2 as maximum.
($1000 x 5 / 3686400) x $8000 = $00B6. As the counter decrements => $100-$B6 = $4A. The ROM tables have $48 as minimum and $4D as maximum.
($1000 x 5 / 4915200) x $8000 = $0088. As the counter decrements => $100-$88 = $78. The ROM tables have $77 as minimum and $7B as maximum.
($1000 x 5 / 6144000) x $8000 = $006D. As the counter decrements => $100-$6D = $93. The ROM tables have $0A as minimum and $12 as maximum - WHICH ARE TOTALLY WRONG.
Contrary to my first verification the compare against the table values is successful for all frequencies but 6,144MHz. If the first comparision against max exits too early, the following compare against min correct this.
I have also verified that 4,9152MHz is running correctly - I did use 4,194304MHz erroneously. Mea culpa. I could also verify that 1,8432MHz works.
The upper frequency limit of my board seems to be 18,432MHz. At least using the crystal osc circuitry without further trimming. 20 and 22,1184MHz did oscillate but the program failed to work. This may also happen because the duty cycle of PHI2 was somewhere between 33/66 .. 40/60.
Next check will be program execution out of flash-eprom. The 39SF010 should arrive soon.
___
edit(1): T1L corrected to TIClo, added try with 1,8432MHz
