How do we handle the loss of 5V CPLDs?

Topics relating to PALs, CPLDs, FPGAs, and other PLDs used for the support or creation of 65-family processors, both hardware and HDL.
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cbscpe
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Re: How do we handle the loss of 5V CPLDs?

Post by cbscpe »

Yes very clever to use only the required number of data Pins to save IO signals. But I normally also have D7 connected to the CPLD to be able to read back status bits and have the N flag set accordingly in one instruction.
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