Posted: Thu May 07, 2009 11:19 am
fachat wrote:
Hi Ruud, did you look at my SD-Card interface?
Thank you very much !!!
YES, this is what I'm looking for: simple and 6502 driven!
Thank you very much !!!
Page 4 of 8
Thank you very much !!!
Posted: Mon May 16, 2011 12:24 pm
I have updated the 65SPI project on my website. I had originally set all of the Slave Select (SS) outputs to default to low. However, most if not all SPI devices have active-low SS pins. I have updated the device to initialize with the SS pins high and updated the datasheet accordingly.
Thanks to Andre for pointing this out. I had corrected this with the SBC-3 and SBC-4 versions, but forgot to go back to the original 65SPI and fix it there.
Here's a link to the 65SPI Page:
http://sbc.rictor.org/io/65spi.html
There's a download link at the bottom of the page.
Daryl
Thanks to Andre for pointing this out. I had corrected this with the SBC-3 and SBC-4 versions, but forgot to go back to the original 65SPI and fix it there.
Here's a link to the 65SPI Page:
http://sbc.rictor.org/io/65spi.html
There's a download link at the bottom of the page.
Daryl
Re: 65SPI
Posted: Sat Dec 31, 2016 12:36 am
One thing to note on the topic of the XC9572 CPLD is that Rochester Electronics are still making them. Trouble with them is that they have a minimum purchase price of $100(probably USD) on them, and unfortunately, they aren't available in PLCC, but it appears that the 3.3v ones(100-pin TQFP only) can be run at 5v(just from a quick look at the datasheet).
These might be viable, but it may be a bit of a pain to do. It would probably need a breakout board(in my ignorant opinion).
Many thanks to Dr Jefyll for bringing up Rochester Electronics, here.
These might be viable, but it may be a bit of a pain to do. It would probably need a breakout board(in my ignorant opinion).
Many thanks to Dr Jefyll for bringing up Rochester Electronics, here.
Re: 65SPI
Posted: Sat Dec 31, 2016 1:08 am
DerTrueForce wrote:
One thing to note on the topic of the XC9572 CPLD is that Rochester Electronics are still making them. Trouble with them is that they have a minimum purchase price of $100(probably USD) on them...
Re: 65SPI
Posted: Sat Dec 31, 2016 4:40 am
Ooh, good thing you picked up on that, BDD. That would've bit someone where it hurt.
Re: 65SPI
Posted: Sat Dec 31, 2016 5:10 am
DerTrueForce wrote:
Many thanks to Dr Jefyll for bringing up Rochester Electronics, here.
BigDumbDinosaur wrote:
Just to be unambiguous, Rochester has a 100 dollar minimum per order, not per item.
"Note: To meet the $100 line minimum the minimum order qty for this part is 295."
"Note: Orders under $250 can be completed if you agree to accept a service charge."
Re: 65SPI
Posted: Sat Dec 31, 2016 5:26 am
A group-buy could make that workable - if 10 people want something, it could be approx $10 each, double that for shipping, and that's a good price for something you can't get anywhere else - even if you end up with lots of parts when you only needed two or three!
Re: 65SPI
Posted: Sat Dec 31, 2016 5:30 am
Dr Jefyll wrote:
DerTrueForce wrote:
Many thanks to Dr Jefyll for bringing up Rochester Electronics, here.
BigDumbDinosaur wrote:
Just to be unambiguous, Rochester has a 100 dollar minimum per order, not per item.
"Note: To meet the $100 line minimum the minimum order qty for this part is 295."
"Note: Orders under $250 can be completed if you agree to accept a service charge."
You are right! I apparently can't see that print due to color, but my wife, who happened to be looking over my shoulder as I was reading your post, could see it. Good thing I have her around. 
Re: 65SPI
Posted: Sat Dec 31, 2016 5:54 am
Hullo, Mrs Dinosaur! Nice to have you with us! 
Re: 65SPI
Posted: Sat Dec 31, 2016 6:11 am
Dr Jefyll wrote:
Hullo, Mrs Dinosaur! Nice to have you with us!
Re: 65SPI
Posted: Sat Dec 01, 2018 7:01 pm
Step 1 of converting the 65SPI from a Xilinx 9572 to Atmel 1504 is finally done. I have a successfully compiled JED file. I had to remove a few features to get it to fit.
Step 2 will be trying to optimize the code to fit a few features back into the design, if possible.
Step 3 will be to actually test a ATF1504 on my SBC-4 using the CF adapter and the ENC28J60 Ethernet module.
Stay tuned. My progress will be slow, but I'll do my best to keep it moving.
Daryl
Step 2 will be trying to optimize the code to fit a few features back into the design, if possible.
Step 3 will be to actually test a ATF1504 on my SBC-4 using the CF adapter and the ENC28J60 Ethernet module.
Stay tuned. My progress will be slow, but I'll do my best to keep it moving.
Daryl
Re: 65SPI
Posted: Sat Dec 01, 2018 8:54 pm
8BIT wrote:
Step 1 of converting the 65SPI from a Xilinx 9572 to Atmel 1504 is finally done. I have a successfully compiled JED file. I had to remove a few features to get it to fit.
Re: 65SPI
Posted: Sat Dec 01, 2018 9:44 pm
Really not sure... it would not provide a fit report for some reason and the error reports I could find talked a bout conflicts with clocks. I suspected the latches I had were the problem so I eliminated the clock divider and associated latches. I had also added some intermediate logic to help simplify some of the state machine logic. The current resource usage is:
I have enough pins but the logic cells are nearly maxed so that may have been one problem.
The current setup has all features except the SPI clock divider. There are 2 clock choices: use PHI2 or an external shift clock. 95% of the time I ran the SPI clock direct from PHI2 on both SBC-3 and SBC-4, so I'm not too worried about losing that option. I really need to go back now and verify all the other logic translated correctly and that the state machine functions are still correct.
Daryl
Code: Select all
Logic Array Block Logic Cells I/O Pins Foldbacks TotalPT FanIN Cascades
A: LC1 - LC16 10/16(62%) 8/16(50%) 0/16(0%) 34/80(42%) (27) 0
B: LC17 - LC32 16/16(100%) 8/16(50%) 1/16(6%) 43/80(53%) (27) 0
C: LC33 - LC48 15/16(93%) 6/16(37%) 1/16(6%) 40/80(50%) (27) 0
D: LC49 - LC64 12/16(75%) 5/16(31%) 0/16(0%) 27/80(33%) (27) 0
Total dedicated input used: 1/4 (25%)
Total I/O pins used 27/32 (84%)
Total Logic cells used 53/64 (82%)
Total Flip-Flop used 37/64 (57%)
Total Foldback logic used 2/64 (3%)
Total Nodes+FB/MCells 55/64 (85%)
Total cascade used 0
Total input pins 9
Total output pins 19
Total Pts 144
The current setup has all features except the SPI clock divider. There are 2 clock choices: use PHI2 or an external shift clock. 95% of the time I ran the SPI clock direct from PHI2 on both SBC-3 and SBC-4, so I'm not too worried about losing that option. I really need to go back now and verify all the other logic translated correctly and that the state machine functions are still correct.
Daryl
Re: 65SPI
Posted: Sun Dec 02, 2018 6:58 am
8BIT wrote:
Really not sure... it would not provide a fit report for some reason and the error reports I could find talked a bout conflicts with clocks. I suspected the latches I had were the problem so I eliminated the clock divider and associated latches. I had also added some intermediate logic to help simplify some of the state machine logic. The current resource usage is:
I have enough pins but the logic cells are nearly maxed so that may have been one problem.
The current setup has all features except the SPI clock divider. There are 2 clock choices: use PHI2 or an external shift clock. 95% of the time I ran the SPI clock direct from PHI2 on both SBC-3 and SBC-4, so I'm not too worried about losing that option. I really need to go back now and verify all the other logic translated correctly and that the state machine functions are still correct.
Daryl
Code: Select all
Logic Array Block Logic Cells I/O Pins Foldbacks TotalPT FanIN Cascades
A: LC1 - LC16 10/16(62%) 8/16(50%) 0/16(0%) 34/80(42%) (27) 0
B: LC17 - LC32 16/16(100%) 8/16(50%) 1/16(6%) 43/80(53%) (27) 0
C: LC33 - LC48 15/16(93%) 6/16(37%) 1/16(6%) 40/80(50%) (27) 0
D: LC49 - LC64 12/16(75%) 5/16(31%) 0/16(0%) 27/80(33%) (27) 0
Total dedicated input used: 1/4 (25%)
Total I/O pins used 27/32 (84%)
Total Logic cells used 53/64 (82%)
Total Flip-Flop used 37/64 (57%)
Total Foldback logic used 2/64 (3%)
Total Nodes+FB/MCells 55/64 (85%)
Total cascade used 0
Total input pins 9
Total output pins 19
Total Pts 144
The current setup has all features except the SPI clock divider. There are 2 clock choices: use PHI2 or an external shift clock. 95% of the time I ran the SPI clock direct from PHI2 on both SBC-3 and SBC-4, so I'm not too worried about losing that option. I really need to go back now and verify all the other logic translated correctly and that the state machine functions are still correct.
Daryl
Re: 65SPI
Posted: Sun Dec 02, 2018 1:45 pm
In my experience, it mainly refuses to spit out a fit report if you have a semantic (not syntactic) error in the CUPL code. E.g. you make reference to a NODE's output, without defining the necessary inputs (such as .d & .ck) for it to know what kind of NODE it is.