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Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Tue Mar 26, 2013 5:20 pm
by ElEctric_EyE
I know it may look strange, but thanks for checking it out...
I use the C accumulator strictly to hold the background color. So that is STCiy (translate: STC ($xxxx),y. i.e.
STore
C accumulator
indirect indexed
y)
and I use the B accumulator strictly for the pixel color. My comments are very lacking I see now.
EDIT: Also whenever I use a macro, there's a '-' in the comment section. I use that to help myself remember what the code should really look like, in spite of the macro.
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Wed Mar 27, 2013 7:21 pm
by ElEctric_EyE
Today I had some other things to do but I was able to finish typing in Daryl's Bresenham Circle program and try it out. First thing I did was comment out anything that had to do with the 6502's MSBs for all the variables, since we're dealing with 16-bit bytes. I'll paste the code. Uh, I just now realized now I could have copied/pasted his code into the assembler.
Code: Select all
CIRCLE LDA RA ;BRESENHAM CIRCLE COURTESY OF DARYL RICTOR @ HTTP://SBC.RICTOR.ORG/
BNE _C1
LDA XC
STA XP
;LDA XC+1
;STA XP+1
LDA YC
STA YP
;LDA YC+1
;STA YP+1
JMP PLTPXL
; INT Y = RADIUS
_C1 LDA RA ;8 BIT RADIUS, CAN BE EXPANDED TO 16 BIT
STA Y1
LDDi $0000 ;-LDD #$0000 ACCUMULATOR IS USED FOR 65C02 STZ, AND IS ALWAYS ZERO IN THIS SUBROUTINE
;STA Y1+1
; INT X = 0
STDzp X1 ;-STD X1
;STDzp X1+1 ;-STD X1+1
; INT F = 1 - RADIUS IF USING 16-BIT RADIUS, THIS SECTION
SEC ;WILL NEED MODIFICATION
LDA #$01
SBC RA
STA FF
;STDzp FF+1 ;-STD FF+1
;BCS _C2
;DEC FF+1
; int ddF_X = 1;
_C2 LDA #$01
STA FX
;STDzp FX+1 ;-STD FX+1
; INT ddF_Y = -2 * RADIUS IF USING 16-BIT RADIUS, THIS CODE SECTION
;STDzp FY+1 ;WILL NEED MODIFICATION ALSO
LDA RA
ASL
STA FY
;ROL FY+1
LDA FY
EOR #$FFFF ;WAS EOR #$00FF
STA FY
;LDA FY+1
;EOR #$FF
;STA FY+1
INC FY
BNE _C3
;INC FY+1
; TGI_SETPIXEL(XC, YC+Y)
_C3 LDA XC
STA XP
;LDA XC+1
;STA XP+1
CLC
LDA YC
ADC Y1
STA YP
;LDA YC+1
;ADC Y1+1
;STA YP+1
JSR PLTPXL
; TGI_SETPIXEL(XC, YC-Y)
SEC
LDA YC
SBC Y1
STA YP
;LDA YC+1
;SBC Y1+1
;STA YP+1
JSR PLTPXL
; TGI_SETPIXEL(XC+Y, YC)
CLC
LDA XC
ADC Y1
STA XP
;LDA XC+1
;ADC Y1+1
;STA XP+1
LDA YC
STA YP
;LDA YC+1
;STA YP+1
JSR PLTPXL
; TGI_SETPIXEL(XC-Y,YC)
SEC
LDA XC
SBC Y1
STA XP
;LDA XC+1
;SBC Y1+1
;STA XP+1
JSR PLTPXL
_CLOOP
; WHILE (X<Y) CALCULATE NEXT PLOT STEP
SEC
LDA X1
SBC Y1
;LDA X1+1
;SBC Y1+1
BCC _C4 ;X<Y
RTS
_C4 ;LDA FF+1
;BMI _C6
;LDA Y1
;BNE _C5
;DEC Y1+1
_C5 DEC Y1
CLC
LDA FY
ADC #$02
STA FY
;TAX
;LDA FY+1
;ADC #$00
;STA FY+1
;TAY
CLC
;TXA
ADC FF
STA FF
;TYA
;ADC FF+1
;STA FF+1
_C6 INC X1
;BNE _C7
;INC X1+1
_C7 CLC
LDA FX
ADC #$02
STA FX
;TAX
;LDA FX+1
;ADC #$00
;STA FX+1
;TAY
CLC
;TXA
ADC FF
STA FF
;TYA
;ADC FF+1
;STA FF+1 ;COMPUTATIONS DONE - NOW PLOT 8 OCTANTS
; TGI_SETPIXEL(XC+X, YC+Y)
CLC
LDA XC
ADC X1
STA XP
PHA
;LDA XC+1
;ADC X1+1
;STA XP+1
;PHA
CLC
LDA YC
ADC Y1
STA YP
;LDA YC+1
;ADC Y1+1
;STA YP+1
JSR PLTPXL
; TGI_SETPIXEL(XC-X, YC+Y)
SEC
LDA XC
SBC X1
STA XP
;LDA XC+1
;SBC X1+1
;STA XP+1
JSR PLTPXL
; TGI_SETPIXEL(XC-X, YC-Y)
SEC
LDA YC
SBC Y1
STA YP
;LDA YC+1
;SBC Y1+1
;STA YP+1
JSR PLTPXL
; TGI_SETPIXEL(XC+X, YC-Y)
;PLA
;STA XP+1
PLA
STA XP
JSR PLTPXL
; TGI_SETPIXEL(XC+Y, YC+X)
CLC
LDA XC
ADC Y1
STA XP
PHA
;LDA XC+1
;ADC Y1+1
;STA XP+1
;PHA
CLC
LDA YC
ADC X1
STA YP
;LDA YC+1
;ADC X1+1
;STA YP+1
JSR PLTPXL
; TGI_SETPIXEL(XC-Y,YC+X)
SEC
LDA XC
SBC Y1
STA XP
;LDA XC+1
;SBC Y1+1
;STA XP+1
JSR PLTPXL
; TGI_SETPIXEL(XC-Y, YC-X)
SEC
LDA YC
SBC X1
STA YP
;LDA YC+1
;SBC X1+1
;STA YP+1
JSR PLTPXL
; TGI_SETPIXEL(XC+X,YC-Y)
;PLA
;STA XP+1
PLA
STA XP
JSR PLTPXL
JMP _CLOOP
PLTPXL LDA XP
STA SCRLO
LDA YP
STA SCRHI
LDY #0
STBiy (SCRLO),Y ;-STB(SCRLO),Y. B ACCUMULATOR IS ALWAYS PIXEL COLOR
RTS
Mild success. The radius is set to 10, and the XC and YC are (100,100).
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Thu Mar 28, 2013 1:55 am
by 8BIT
Looks like you got to the start of the loop (0,90,180,270 deg points got plotted correctly). It's a start!
Daryl
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Fri Mar 29, 2013 1:56 am
by ElEctric_EyE
Looks like you got to the start of the loop (0,90,180,270 deg points got plotted correctly). It's a start!
Daryl
I had nothing at first. Then 1 pixel, then 2. Then 4, which is when I posted...
I'm running through your code now using ISim, and skipping all the real world stuff like clear screen and character plotting for the timer.
Hopefully I can do this one step at a time and post. It's a dual step here where I have to understand what's going on in your program, then convert to 65O16. I guess I can consider ISim my real world emulator. I will make more progress soon.
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Fri Mar 29, 2013 2:18 pm
by 8BIT
I took a quick look but will need more time to study the changes. I think there is some decision making code here that needs to be addressed. Will work on it over the weekend.
Code: Select all
_C4 ;LDA FF+1
;BMI _C6
;LDA Y1
;BNE _C5
;DEC Y1+1
Daryl
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Fri Mar 29, 2013 10:32 pm
by ElEctric_EyE
Thanks for taking some of your time out to do that, I appreciate it!
The few minutes I have after a long day at work don't seem to be very fruitful. Chances are progress won't be made on my end til tue or wed.
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Sat Mar 30, 2013 9:19 pm
by 8BIT
ok, I think this will work. I removed the commented-out lines for clarify. Let me know how this works.
Daryl
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Sat Mar 30, 2013 11:19 pm
by ElEctric_EyE
Ah, I see you've totally redone _C4. Was just checking. Trying now...
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Sun Mar 31, 2013 12:01 am
by ElEctric_EyE
No change in the graphics, however, the timer now reads at 0.00000304 which is .1uS faster. Not sure if this makes sense. Too much going on in the next few days... ^^^ Check PM.
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Sun Mar 31, 2013 2:53 pm
by ElEctric_EyE
Forgot I had Easter Sunday off, heh.
With a clear mind and using ISim, I was able to track down where it is exiting:
Code: Select all
_CLOOP
; WHILE (X<Y) CALCULATE NEXT PLOT STEP
SEC
LDA X1
SBC Y1
BCC _C4 ;X<Y
RTS
The carry is set with X1=0, and Y1=RA=10, so it is not branching.
EDIT: Looks like another problem with the .b core. Changing the BCC to a BCS plots the circle, then continues off into infinity. The SBC is not resetting the Carry flag. I'll check this out next.
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Sun Mar 31, 2013 4:50 pm
by ElEctric_EyE
Looking again at the
ALU the case where A-B. Considering if A=$0000 and B was $FFFF, then value of temp_BI was just be $0000 and temp would be $0000 or $0001 depending on the CarryIn. I think temp_BI needs to be expanded to 17-bits, that would result in a value of $10000. Then modify the CarryOut to toggle the CarryIn if (temp_BI[16]) is set.
Code: Select all
always @* begin
case( op[3:2] )
2'b00 : temp_BI = BI; // A+B
2'b01 : temp_BI = ~BI; // A-B
2'b10 : temp_BI = logical; // A+A
2'b11 : temp_BI = 0; // A+0
endcase
end
//always @(logical or temp_BI or adder_CI)
always @*
temp = logical + temp_BI + adder_CI;
..........
// calculate the flags
always @(posedge clk)
if( RDY ) begin
......
......
......
CO <= (shiftrotate ? tempshifted[dw] : temp[dw]);
......
end
I've expanded the temp_BI register and it looks good. Working on the Carry.
Sound logical?
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Sun Mar 31, 2013 5:24 pm
by Arlet
In the 8 bit core, the temp_BI signal is only 8 bits, but I don't think there's a problem with the carry. Not sure what the problem is.
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Sun Mar 31, 2013 5:41 pm
by MichaelM
I generally capture the output carry for an adder in a vector that's one bit wider than the operands. I don't think that you need to increase the size of the input data, but simply expand the size of your output by one bit. The extra bit will be the carry out of the summer. The following code snippet is an example;
Code: Select all
module Add(
input [15:0] A, // Adder Input A
input [15:0] B, // Adder Input B
input Ci, // Adder Carry In
output [15:0] Sum, // Adder Sum <= A + B + Ci
output Co // Carry Out
);
assign {Co, Sum} = A + B + Ci;
endmodule
It results in the synthesis of a 16-bit adder with a carry input and a carry output. The carry output will be assigned to Co.
========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 1
16-bit adder carry in/out : 1
========================================================================
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Sun Mar 31, 2013 5:49 pm
by ElEctric_EyE
Thank you both! I was going to ask Arlet the following, but I think I've found my problem, in the middle of posting, in the opcode decoding for the adc_sbc flag.
In your core, when it executes any opcode that sets the OP_SUB flag for the ALU.v to do a subtraction, in which the ALU would have to change the C flag going back into the cpu, I don't see how that CO signal works it way back into the cpu.v for the OP_SUB opcodes.
Code: Select all
/*
* Update C flag when doing ADC/SBC, shift/rotate, compare
*/
always @(posedge clk )
if( shift && state == WRITE )
C <= CO;
else if( state == RTI2 )
C <= DIMUX[0];
else if( ~write_back && state == DECODE ) begin
if( adc_sbc | shift | compare )
C <= CO;
else if( plp )
C <= ADD[0];
else begin
if( sec ) C <= 1;
if( clc ) C <= 0;
end
end
The adc_sbc is for the addition opcodes
EDIT: In comparing the 2 cores, I think I just saw my error. One I think I've had from the very beginning of tinkering with Verilog and your core. I had misunderstood your adc_sbc flag to be set for
only the ADC opcodes, which I always thought was strange. Which now I see it is strange, because it's wrong.
Re: Concept & Design of 3.3V Parallel 16-bit VGA Boards
Posted: Sun Mar 31, 2013 6:49 pm
by ElEctric_EyE
It works!
I had to loose the random number generator so the project would fit, luckily the timer still fit after 15 runs of smartexplorer!
I timed a circle with radius 150 @.6mS. Very nice looking circle.