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module SRAMif( input cpuWE,
					input [31:0] cpuAB,
					input [15:0] ZPP,				//from CPU, zeropage pointer
					input [15:0] SPP,				//from CPU, stackpage pointer
					output reg ram1CS = 0,
					output reg ram1WE = 0,		//pre-init to '0', not selected
					output reg ram2CS = 0,
					output reg ram2WE = 0,		//pre-init to '0', not selected
					output reg rom1CS = 0
					);

// address decoding for internal blockRAMs
wire [15:0] ZPP;
wire [15:0] SPP;

always @* begin
	ram1WE <= ( !ram1CS && cpuWE );
	ram2WE <= ( !ram2CS && cpuWE );
	if ( (cpuAB >= {ZPP,16'h0000}) && cpuAB <= ({ZPP,16'h03ff}) )		//1Kx16 zeropage RAM address decode w/ZPP reg as the MSB pointer
		ram1CS <= 0;
		else ram1CS <= 1;
	if ( (cpuAB >= {SPP,16'hfc00}) && cpuAB <= ({SPP,16'hffff}) )		//1Kx16 stackpage RAM address decode w/SPP reg as the MSB pointer
		ram2CS <= 0;
		else ram2CS <= 1;
	if ( (cpuAB >= 32'hffff_f000) && (cpuAB <= 32'hffff_ffff) )		//4Kx16 'initialized RAM' ROM address decode
		rom1CS <= 0;
		else rom1CS <= 1;
end

Code: Select all

module CPU( input clk,          // CPU clock 
				input rst,            // reset signal
				output reg [aw-1:0] addr, // address bus
				input [dw-1:0] din,      // data in, read bus
				output reg [dw-1:0] dout,     // data out, write bus
				output reg we,              // write enable
				output reg [dw-1:0] ZPPout,	//Zeropage pointer
				output reg [dw-1:0] SPPout,	//Stackpage pointer
				input IRQ,              // interrupt request
				input NMI,              // non-maskable interrupt request
				input RDY               // Ready signal. Pauses CPU when RDY=0  );
				);
......
......
assign ZPPout = QAWXYS[20];
assign SPPout = QAWXYS[21];