Shopping list for 6502 experiments

[nrrd]

I think this is done now. Many thanks to all who contributed.
I've had fun exploring this but I also think I'm going to start exploring the 65816 now.
I like to build just one thing, rather than having multiple projects!
If I could build something equivalent to a fast (12 to 16 MHz) Apple IIGS, I'd be happy.

[BigDumbDinosaur]

nrrd wrote:

I was thinking about this and it occurred to me that the 6502 is little endian...

Not sure what endianess has to do with the banking scheme.  The U5 bank register only handles a byte.

Quote:

...so the way it is set up at the moment is:

Code: Select all

$0000 = ROM BANK 1
$8000 = ROM BANK 2
$4000 = ROM BANK 3
$C000 = ROM BANK 4

$0001 = RAM BANK 1 (mirrored low RAM)
$8001 = RAM BANK 2
$4001 = RAM BANK 3
$C001 = RAM BANK 4

That’s not how I am interpreting it.

Your bank register is mapping 64K segments because each possible combination of bits 0-3 affects a RAM or ROM address line that is A15 or higher.  Here’s how I see those bits setting the upper memory address range (I’m ignoring the I/O block for discussion’s sake):

Code: Select all

                                    Upper Memory
BITS 0-3   A15   A16   A17   A18   Address Range
————————————————————————————————————————————————
 %0000      0     0     0     0    008000-008FFF
 %0001      1     0     0     0    008000-00FFFF
 %0010      0     1     0     0    018000-018FFF
 %0011      1     1     0     0    018000-01FFFF
 %0100      0     0     1     0    028000-028FFF 
 %0101      1     0     1     0    028000-02FFFF
 %0110      0     1     1     0    038000-038FFF
 %0111      1     1     1     0    038000-03FFFF
 %1000      0     0     0     1    048000-048FFF
 %1001      1     0     0     1    044000-04FFFF
 %1010      0     1     0     1    058000-058FFF
 %1011      1     1     0     1    058000-05FFFF
 %1100      0     0     1     1    068000-068FFF
 %1101      1     0     1     1    068000-06FFFF
 %1110      0     1     1     1    078000-078FFF
 %1111      1     1     1     1    078000-07FFFF
————————————————————————————————————————————————

Also, as you have it wired, if bit 7 of the pattern written to the register is cleared, ROM will be selected.  With bit 7 set, RAM will be selected.

Quote:

What I really want is:

Code: Select all

$0000 = ROM BANK 1
$0001 = ROM BANK 2
$0002 = ROM BANK 3
$0003 = ROM BANK 4

$8000 = RAM BANK 1 (mirrored low RAM)
$8001 = RAM BANK 2
$8002 = RAM BANK 3
$8003 = RAM BANK 4

I think I just need to reorder the output from the latch to do this.

See my above table.  What you want is not possible as you have it wired.

Quote:

BigDumbDinosaur wrote:

Speaking of U5, I think you have a booby-trap waiting for you in how you are accessing it...

I was thinking about this when I couldn't sleep at 5:30 this morning. I can just qualify it with the write line, but I have to make sure I haven't changed the phase of the clock.

You need to invert the /WB signal and use that to clock the bank register.

[nrrd]

Thanks for your reply again.

Quote:

Not sure what endianess has to do with the banking scheme. The U5 bank register only handles a byte.

I was getting myself confused. What I meant was whether D0 or D7 was the least significant bit. I've gone back to the datasheet and confirmed that D0 is the LSB. Now that I have sorted that out, I realised I was correct with my first drawing.

Quote:

Your bank register is mapping 64K segments because each possible combination of bits 0-3 affects a RAM or ROM address line that is A15 or higher.

No, sorry, A15 selects the lower 32K when 0, and the upper 32K when 1, so by switching A15 to activate the banking scheme, I am mapping 32K segments.

Your table is almost correct. I think there may be copy-paste errors.
It should be:

Code: Select all

                                    Upper Memory
BITS 0-3   A15   A16   A17   A18   Address Range
————————————————————————————————————————————————
 %0000      0     0     0     0    000000-007FFF
 %0001      1     0     0     0    008000-00FFFF
 %0010      0     1     0     0    010000-017FFF
 %0011      1     1     0     0    018000-01FFFF
 %0100      0     0     1     0    020000-027FFF
 %0101      1     0     1     0    028000-02FFFF
 %0110      0     1     1     0    030000-037FFF
 %0111      1     1     1     0    038000-03FFFF
 %1000      0     0     0     1    040000-047FFF
 %1001      1     0     0     1    044000-04FFFF
 %1010      0     1     0     1    050000-057FFF
 %1011      1     1     0     1    058000-05FFFF
 %1100      0     0     1     1    060000-067FFF
 %1101      1     0     1     1    068000-06FFFF
 %1110      0     1     1     1    070000-077FFF
 %1111      1     1     1     1    078000-07FFFF
————————————————————————————————————————————————

I wrote a quick Python program to confirm this.

Quote:

Also, as you have it wired, if bit 7 of the pattern written to the register is cleared, ROM will be selected. With bit 7 set, RAM will be selected.

This is as desired. When the latch is reset, for example at boot, then the ROM will be selected. This allows the 6502 to read the starting PC from the ROM at 0xFFFC and 0xFFFD.

Quote:

You need to invert the /WB signal and use that to clock the bank register.

Thanks, I've incorporated that into the latest schematic.

[GARTHWILSON]

nrrd wrote:

I was getting myself confused. What I meant was whether D0 or D7 was the least significant bit. I've gone back to the datasheet and confirmed that D0 is the LSB. Now that I have sorted that out, I realised I was correct with my first drawing.

I'm not sure it's a hard-and-fast rule; but "LSB" (all cap.s) is usually "least significant byte," and "lsb" (lower-case) is "least significant bit."