Issues with 6502?

[Dr Jefyll]

Niek6502 wrote:

I thoroughly enjoy this "back to basics" experience

Wonderful! Nice to hear you're finding the endeavor rewarding!

About this...

... I'd suggest that you not ground the /OE on the EEPROM. Instead, I'd drive /OE with an inverted version of PHI2 (which you could obtain by using an additional inverter section, or -- less preferably -- simply getting it directly from the oscillator).

It's because ideally we want all devices which can drive the data bus to refrain from doing so in the first half of every cycle when PHI2 is low. The resulting dead period acts as a timing cushion, guaranteeing a graceful and glitch-free handover as various devices successively take control of the bus. (And the bus wouldn't transfer any useful data in the first half-cycle anyway. ) Refraining from driving the bus when PHI2 is low is a policy which the CPU itself -- and all 65xx peripherals, including your VIAs -- observe. It's desirable, though not crucial, that your EEPROM do the same.

BigDumbDinosaur wrote:

for Schmitt-triggered inverters [...] It’s not uncommon for the input voltage at which the output switches from low to high to be substantially different than when the output switches from high to low.

Right. That substantial difference between the high-going and low-going trigger points is known as hysteresis, and it's a defining feature. Gates whose high-going and low-going trigger points are virtually identical aren't Schmitt triggers (although it's possible they may approach a Schmitt's all-or-nothing "snap action").

-- Jeff

[BigDumbDinosaur]

Dr Jefyll wrote:

BigDumbDinosaur wrote:

for Schmitt-triggered inverters [...] It’s not uncommon for the input voltage at which the output switches from low to high to be substantially different than when the output switches from high to low.

Right. That substantial difference between the high-going and low-going trigger points is known as hysteresis...

I did say that in my post. 

Quote:

If you carefully read the data sheet, you will see that input hysteresis for Schmitt-triggered inverters can be all over the map.

Dr Jefyll wrote:

It's because ideally we want all devices which can drive the data bus to refrain from doing so in the first half of every cycle when PHI2 is low. The resulting dead period acts as a timing cushion, guaranteeing a graceful and glitch-free handover as various devices successively take control of the bus.

That is something I have been “harping” about for eons.  Aside from the potential for data bus contention that a continuously-grounded /OE can bring about, devices that have separate /CS and /OE control inputs typically exhibit better timing characteristics if /OE is used to gate the device’s output.  This information is often buried in one of the timing diagrams in the data sheet.  A similar situation exists for many devices that are writable, e.g., an SRAM.

The best way to handle non-65xx peripheral silicon is arranging for the glue logic to assert /CS as soon as a valid address is present, and qualify /OE and /WE with Ø2 so neither of those signals can go low while Ø2 is low.  Doing so maximizes the time the addressed device has to get ready for access and in the case of a write cycle, prevents a wild write during the time when the address bus is changing following the fall of the clock.

Read/Write Qualified by Ø2

Note that the above circuit is not applicable to 65xx devices, which “understand” the 6502 bus cycle.  For them, chip select and read/write must never be qualified by Ø2.

[Dr Jefyll]

BigDumbDinosaur wrote:

That is something I have been “harping” about for eons.

Yup. I'm on the same page with you in this regard.

BigDumbDinosaur wrote:

Dr Jefyll wrote:

BigDumbDinosaur wrote:

for Schmitt-triggered inverters [...] It’s not uncommon for the input voltage at which the output switches from low to high to be substantially different than when the output switches from high to low.

Right. That substantial difference between the high-going and low-going trigger points is known as hysteresis...

I did say that in my post. 

Sorry if my emphasis wasn't clear. Yes, we agree it's known as hysteresis. My small-ish quibble regards your remark that, "It’s not uncommon" [etc]. This misses the mark somewhat, as it's true in all cases that a Schmitt-trigger gate's positive-going and negative-going thresholds will be substantially different. That's the defining feature of a Schmitt trigger gate.

-- Jeff

[Niek6502]

Thank you for keeping to chime in! I had one more inverter gate available in my glue setup, so that was an easy change. I have updated the breadboard and the schematic. On my board, the clock, reset setup (still to update) and glue are fairly self-contained, so I can easily change these out for a different setup. At some point, I want to add a PIC, a CPLD and/or an ATmega to poke around with (mostly to see what they can do), maybe have one of these handle the glue glue tasks to "clean up" the hardware (or completely mess it up, but it will be easy to revert to this working setup).

No doubt I will run into issues there (no worries, I do plan on tackling all of that myself), but for met that is the challenge and fun of all this.

Thanks!

-Niek.

[L0uis.m]

Hello 0010 all,

Looking at the schematic above, it occurred to me there is some ambiguity in naming the clock in- and outputs of a 65(C)02.
All data sheets I have (except WDC) use: Φ0 for clock input, Φ1 for inverted clock output and Φ2 for non-inverted clock output.

This razed some questions for me: what is the difference between those, is the Φ2 from a WDC the same as a Φ0 from all the other 65's, and what about the clock outputs, are they different as well

In the original Atom the Φ2 (input) from the 65(C)22 gets it's signal (via two inverters) from the µP's Φ2 (output). In the schematic above the two 65(C)22 get theirs from the same clock line that supplies the µP (Φ0).

What's going on (t)here, is this ambiguity discussed earlier in this thread, or elsewhere in this forum, and if so, could someone please point out (link) where

[GARTHWILSON]

I suppose it comes from the fact that WDC recommends that the Φ2 input to the processor be the same signal as to the Φ2 input to the rest of the system, and that Φ2in is roughly in phase with Φ2out except that there's a little offset from internal gate delays.

Quote:

May your wires be long

That's like saying "I hope you shoot nice high golf scores."  In this work, you generally want connections as short as you can get them, especially ground connections.  A wire-wrap wire has 20nH of unwanted inductance per inch, and going to a fatter wire has very little effect on inductance unless you really step it up hugely.

[BigDumbDinosaur]

L0uis.m wrote:

All data sheets I have (except WDC) use: Φ0 for clock input, Φ1 for inverted clock output and Φ2 for non-inverted clock output.

WDC’s naming of those signals is the convention, since WDC was the entity that developed the 65C02.  Rockwell, Synertek et al were licensees.

Quote:

This razed some questions for me: what is the difference between those, is the Φ2 from a WDC the same as a Φ0 from all the other 65's, and what about the clock outputs, are they different as well

Ø0 on other 6502 data sheets corresponds to PHI2 on the WDC data sheet.

As Garth noted, WDC recommends you use the master clock source to drive the MPU and 65xx devices that must be clocked, e.g., 65C21, 65C22, etc..  The 65C02’s internal timing is referenced to Ø2 in (pin 37 on the DIP).  They further recommend you do not use Ø1 out and Ø2 out in new designs.  The lag between Ø2 and the clock output signals is no longer specified, nor is it tested during production.  Furthermore, there is no guarantee that Ø1 out and Ø2 out are exactly 180 degrees out of phase.

This information is in the data sheet in section 3.8 on page 10, and as a footnote on page 26.

65c02.pdf

WDC 65C02 Data Sheet

(382.89 KiB) Downloaded 63 times

[L0uis.m]

Hello Garth and BDD,

GARTHWILSON wrote:

Quote:

May your wires be long

That's like saying "I hope you shoot nice high golf scores."  In this work, you generally want connections as short as you can get them, especially ground connections.  A wire-wrap wire has 20nH of unwanted inductance per inch, and going to a fatter wire has very little effect on inductance unless you really step it up hugely.

The quote "May your wires ..." originates form an article in the Dutch Atom Nieuws magazine about extending the flat-cable between an Atom and a floppy drive. If I remember well, the original cable was only a few centimetre. With that cable the drive could only stand right behind the Atom in front of the monitor. By extending the cable it could be placed beside the monitor. That article ended with this quote.

BigDumbDinosaur wrote:

WDC’s naming of those signals is the convention, since WDC was the entity that developed the 65C02.  Rockwell, Synertek et al were licensees.

Ø0 on other 6502 data sheets corresponds to PHI2 on the WDC data sheet.

As Garth noted, WDC recommends you use the master clock source to drive the MPU and 65xx devices that must be clocked, e.g., 65C21, 65C22, etc..  The 65C02’s internal timing is referenced to Ø2 in (pin 37 on the DIP).  They further recommend you do not use Ø1 out and Ø2 out in new designs.  The lag between Ø2 and the clock output signals is no longer specified, nor is it tested during production.  Furthermore, there is no guarantee that Ø1 out and Ø2 out are exactly 180 degrees out of phase.

This information is in the data sheet in section 3.8 on page 10, and as a footnote on page 26.

This is all very confusing to me. As far as I know MOS Technology was founded in 1969, later in 1978 WDC was founded (by a former MOS Technology employee), so it seems more likely to me than that WDC did not set, but changed the standard. Besides, I grew up with Φ0, Φ1 and Φ2, and to me they are indicating (the hierarchy of) the signals much clearer than Φ2, Φ1 and Φ2, partly because in the later case there is a mix up of the signal names, by some the clock input is named just Φ2 and by others Φ2I, similar the two outputs are labelled with or without the suffix "O" (sometimes even combinations of with and without suffix are used).

Appart from all that:
Is it possible (or even better) to connect the clock input (Φ2) of a 65(C)22 VIA with the same signal that goes to the clock input (Φ0 aka Φ2) of a 65(C)02 µP, regardless of ICs being CMOS (C) or not

I'm not very familiar with the BBC, but am I right that's the way it is wired in a Beeb, and can it also be done that way in an Atom

[Dr Jefyll]

BigDumbDinosaur wrote:

WDC’s naming of those signals is the convention, since WDC was the entity that developed the 65C02. Rockwell, Synertek et al were licensees.

Quote:

As far as I know MOS Technology was founded in 1969, later in 1978 WDC was founded (by a former MOS Technology employee), so it seems more likely to me than that WDC did not set, but changed the standard.

Compared to NMOS 6502s which predated WDC, yes, L0uis.m, it's true that the manufacturer's terminology in reference to the clock pins did change (and also the recommendation of what to do with those pins).

Understanding the recommended connection is moderately important. (But I don't see much point in debating whether one pin naming convention or the other should be considered "correct" or "standard." Certainly WDC's convention is standard for WDC, but I wouldn't bother pursuing the point any further.)

I do kinda understand why WDC made the naming change, though.

For technical reasons, they'd decided that having their CPU be the middleman, and thus the source of Phi2 for other devices in the system, was not the best arrangement. Instead they suggested that it'd be better if all devices in the system -- including the CPU -- should simply accept Phi2 as an input.

And I can see potential for confusion if the name of pin 37 were not changed. Some folks would find it strange that the signal driving their VIA's Phi2 input would also connect to CPU pin 37... whose name cites Phi0. I suspect that's why WDC renamed pin 37 as PHI2. (They also stopped using the Φ character in all three of the pin names, substituting PHI instead.)

It's important to be clear that the pin functions didn't change. Pin 37 is always an input, and pin 39 and pin 3 are always outputs, although the latter two won't necessarily get used (at least not externally -- but the internal signals fed to pin 39 and pin 3 do get used internally by the CPU).

Finally, it's perhaps a simplification for me to have drawn inverters to represent the internal circuitry, as there may be some degree of pulse shaping going on as well. But inverters do accurately give the general idea.

-- Jeff

[BigDumbDinosaur]

Dr Jefyll wrote:

Understanding the recommended connection is moderately important. (But I don't see much point in debating whether one pin naming convention or the other should be considered "correct" or "standard." Certainly WDC's convention is standard for WDC, but I wouldn't bother pursuing the point any further.)

True that.  As long as one understands which pin gets connected to what, one can call them anything one likes.

Quote:

For technical reasons, they'd decided that having their CPU be the middleman, and thus the source of Phi2 for other devices in the system, was not the best arrangement. Instead they suggested that it'd be better if all devices in the system -- including the CPU -- should simply accept Phi2 as an input.

I suspect, but don’t know for sure, that their recommendation has to do with the much higher speeds at which modern 65C02 incarnations can be run.  Perhaps the skew between Ø2 in and the two outputs was a concern as the clock was ramped up.  Or maybe their production people are just lazy and don’t feel like testing those outputs. 

BTW, Jeff, I must commend you for your illustrations.  They are always well-done and even make sense to me. 

To L0uis.m, there’s some history about why those clock outputs exist.

Back in the early days of the 6502, the clock signal was often generated by use of a crystal hooked up with some inverters and capacitors, like this (illustration from Garth’s website).  The resulting signal didn’t have a lot of oomph, especially since the inverters would have been early incarnations of 74LS logic, or even earlier, e.g., 7404 or 74S04.  Too much loading could weaken the signal to where oscillation would falter.  The Ø1 out and Ø2 out signals were provided to avoid the loading that would be present from clocking other 65xx hardware, and possibly bus drivers and/or transceivers.  The latter parts were in common use at the time to deal with the limited fan-out of the 6502’s buses and the loading imposed by 74LS inputs.

Quote:

(They also stopped using the Φ character in all three of the pin names, substituting PHI instead.)

Back in the olden days (1980s and early 1990s), WDC’s data sheets were typewritten—Φ doesn’t exist on most typewriters (it’s from the Greek alphabet, and is pronounced “fi”).  On the other hand, Rockwell’s data sheets were all typeset, and Φ appears in them in references to the clock.  I use Ø, which is the electrical engineering symbol for phase, e.g., one often sees 3Ø (pronounced “three phase”) used in industrial motor control schematics.  On a typewriter, it is possible to create the Ø symbol as a digraph by typing O, backspacing, and then typing /.  That was probably too much trouble for whomever typed up WDC’s data sheets. 

65c02_1984_rockwell.pdf

Rockwell 65C02 Data Sheet from 1984

(13.12 MiB) Downloaded 70 times

In this 1984 Rockwell data sheet, Φ is used to represent the clock signal.

65c02_1990.pdf

WDC 65C02 Data Sheet from 1990

(2.32 MiB) Downloaded 90 times

In this 1990 WDC data sheet, PHI is used to represent the clock signal, with the input being called PHI2.

6500_mostech_1980.pdf

MOS Technology 6502 Data Sheet from 1980

(16.69 MiB) Downloaded 44 times

In this typeset MOS Technology 6502 data sheet from 1980, Ø is used to reference the clock, with Ø0 being the clock input to the MPU.

[L0uis.m]

Hello 0010 all,

I never intended to put the naming of pins/signals to discussion, merely tried to express my train of flabbergasted thoughts (see edits in my last writing above).

My target is to try to understand what is what and what to connect to what, because I am trying to upgrade an Atom step by step. The differences in naming by different manufacturers and authors through the years, just have sent me into a hazy maze of daze.

BDD wrote, the Φ2 output was created because the generated clock signal had too little oomph. If so, I don't understand why that Φ2 output had no oomph either !
As far as I know the Φ2 output from a 6502 has a fanout of barely more than one, I have been taught that's why it needed to be buffered by those two gates in an Atom !
An other thing I was taught is that the delay was crucial for correct read- and write-timing, hence a circuit with R/NW and Φ2 (output from 6502) as inputs to generate NRDS and NWDS signals in an Atom.

I just wanted to start with replacing a 6502 in an Atom board with a WD65C02 (performing some minor alterations because of different/extra pin functions) , later folowed by replacing memory etc., but now I'm no longer sure if that's possible. It seems to me that I must throw all that (knowledge) overboard and start from blank again.

[Dr Jefyll]

L0uis.m wrote:

I am trying to upgrade an Atom step by step.

Sounds like a worthy project. And fun! But it's probably best if you start a new topic for it. That way, there'll be no distraction from what Niek6502 wants to discuss here.

In the first post of the new thread you can describe what you hope to do, and maybe describe some of the issues you anticipate dealing with. You've hinted at some of that already here, but mention it again in the first post of the new thread. (And maybe make one final post in this thread, linking to the new one).

L0uis.m wrote:

In the original Atom the Φ2 (input) from the 65(C)22 gets it's signal (via two inverters) from the µP's Φ2 (output).

Please also include the Atom schematic, or a link to it. Basic info like this is best to include right away, so folks don't have to ask you for it later.

-- Jeff

[BigDumbDinosaur]

Dr Jefyll wrote:

Sounds like a worthy project. And fun! But it's probably best if you start a new topic for it.

Yep!  And just keep adding to it as you make progress.  That sort of “builder’s log” can be useful not only to others who are interested in your project, but useful to you when you have trouble recalling some obscure detail.

Quote:

Please also include the Atom schematic, or a link to it.  Basic info like this is best to include right away, so folks don't have to ask you for it later.

Attaching the schematic to your post is best.  Off-site links seem to rot out after a while.

I’d be interested in seeing the Atom’s schematic, if for no other reason than pure curiosity.  BTW, please post schematics in monochrome so partially-colorblind blokes such as moi can read them. 

[Niek6502]

Dr Jefyll wrote:

But it's probably best if you start a new topic for it. That way, there'll be no distraction from what Niek6502 wants to discuss here.

The initial reply was somewhat relevant, as L0uis.m was "triggered" by one of the schematics. But yes, I agree, the current direction would be best discussed in a new topic.

Speaking of topics (and not meaning to go off-topic here), I have been reading quite a few threads on this forum, and I am blown away by the focus and technical knowledge here. I frequent various "specialized" forums, mostly in relation to one of my jobs (selling Lego parts), and discussions there tend to veer off into silly quabbles about mustard and pineapple pizza. One of the threads here (just to mention one) is about "the Cactus". Amazing. I pulled up his web site, and the last post on there was in fact just a few hours old.

So much to digest, and so little time. Thanks all for indulging a white-haired HW newbie.

-Niek.

[BigDumbDinosaur]

Niek6502 wrote:

I frequent various "specialized" forums, mostly in relation to one of my jobs (selling Lego parts), and discussions there tend to veer off into silly quabbles about mustard and pineapple pizza.

Mustard and pineapple pizza?  Egads!  Sounds like the makings of a very effective emetic.