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/*==============================================================================

   UART     Sample verilog UARTS on the internet appear to be written by
            chatgpt and copied by engineering students.  I cannot possibly
            express my disgust in the level of what passes for engineering!

            These were based on a pretty nice OPC design, and I've been tweaking them.
 
            Current UART-TX is 28 LUTs and 26 registers.
*/

module UartTX1(
    input   clk,
    input   [12:0] timebase,        // clock / baud rate
    output  txout,                  // connect to the output pin
    input   [7:0] din,              // only store when ready is asserted
    input   load,                   // after storing, ack so the UART knows
    output  ready                   // when 1, uart is ready for data
);                                        // I whittled the frame to 11 bits: a zero
                                          // start bit, a stop bit, and an extra bit
                                          // where idx immediately signals READY.
 reg [10:0] frame = 11'b11_11111111_1;    // Data is deposited at 8:1, and the entire
 reg [3:0] idx = 0;                       // frame is bit-indexed by idex for xmission.
 assign ready = (idx==10) ;               // idx gets stuck at 10, outputting high and
 assign txout = frame[idx];               // setting the READY pin
 reg [12:0] cnt;                    // only 11 bits used, bit 12 is set when
                                    // counter goes negative.  Cheaper than 0 detect.
 always @ (posedge clk)
  if(ready) begin                   // only when we are free we can consider a load.
    if(load) begin                           // upon load we fill the frame and reset
      frame[10:0] <= {2'b11,din[7:0],1'b0};  // the index, releasing ready and starting
      idx <= 0;                              // the clock.  Until then, we are idle,
     end                                     // with idx=10 and 1 on the wire.
  end
  else                              // if we are transmitting, cnt is decremented until
    if(cnt[12]) begin               // -1 at which point we reload it and bump the bit
      cnt <= timebase;              // index for the next bit.
      idx <= idx+1;                 // Note that when it hits 10, ready will stop us at
     end                            // the next clock, with count pretty much full.
    else                            // Notice that when we load a frame, we do not set
      cnt <= cnt-1;                 // the count -- we know it's full (avoiding a mux).
endmodule

// At startup the counter is set to 0 and will immediately flip.  
// index is likewise set to zero, -- we will shift out 10 one bits and halt.