6502.org

Cleaning up my messy lab and found this updated rev1 PC board that fixed the RAM footprint. However, I wasn't able to get it to run past 33MHz even with 10nS RAM. My original wire-wrapped design that ran to 36MHz must've been a outlier.

While checking out the design margin of rev1 VGA65, viewtopic.php?f=4&t=6517&start=30#p115070 I thought about the overclocking experiment so I changed the original VGA65 CPLD equations to that of the overclock platform. I also disconnected the CF disk to reduce data bus load. Bootstrap is done via the serial port using multi-stage bootstrapping that boots from a small ROM resided in CPLD to load a 256-byte HEX loader which, in turn, loads the application software. I found the rev1 VGA65 can run at 36.8Mhz at 5.0V, room temperature. Encouraged by the result, I built second board (picture below) that ran error free at 36Mhz passing memory diagnostic and Dormann instruction tests, but failed the memory diagnostic intermittently at 36.8Mhz.
This is the results I was shooting for 2 years ago; I was looking for a production W65C02 with fast RAM and decode that can run up to 36Mhz. It happened accidentally.
Bill

Well, congrats Bill! Sometimes the best things happen by accident Or, perhaps it was destiny!

It is interesting that your board design here isn't specifically designed for this operation like the previous one was: stacking chips for shortest traces, etc. Do you think the CF disk was somehow slowing it down, perhaps with bus conflict or something?

Good update! Great work (even if by accident)

Chad

It turns out the top speed of VGA65 rev1 dropped to 33 MHz once CF is added. Except for the one wire wrapped outlier, all my other attempts that have 6502, RAM, CPLD, and CF maxed out around 32 or 33 MHz. Reducing bus loadings is the key to higher speed, but a reasonable computer needs memory, I/O and mass storage, so that minimum set of components determines the minimum bus loadings. I can replace parallel CF disk with SPI SD card, but it is very easy to bootstrap from CF, not so easy to bootstrap from SD, so now I need a ROM to initialize SD; no saving on bus loadings when all is said and done. Low to mid 30’s MHz seemed to be the practical limit of W65C02 computers.
Bill

I agree that buffering the Ø2 clock might help... but in regard to customizing the lengths of certain data paths I'm even less optimistic than BDD.

However, I'm (belatedly) posting to remark on the handicap posed by the CPU's 40-pin DIP package (which results in longer connections within the package, and -- even more regretably -- only one ground pin). To remedy both of these drawbacks, I'm sure plasmo would've used a PLCC or FlatPack if the PCB were designed specifically for overclocking.

But, given that it uses the 40-pin CPU, it's lucky that the system *does* have minimal capacitive loading (ie, not much IO)... because increased capacitive loading would cause the on-die Gnd rail to more drastically deviate from outside-world ground... this exacerbation resulting from the comparatively high inductance of just a single ground pin.

-- Jeff

/me rummages in the drawer for the perfect ground... perhaps it's there, behind the vacuum packed spherical cow, or maybe under the box of unobtanium?

Neil

Interesting thing about the VGA65 rev1 design is not only 6502 in DIP40 package, but the pc board is only 2-layer and autorouted without any attention to matching length nor minimizing the clock trace. My standard practice with 2-layer pc board is reduce the board size by 0.05” all around, autoroute the smaller board, then expand the board by 0.05” and manually add a power ring and ground ring. This provides additional power and ground paths and works surprisingly well.
Bill

As inexpensive as four-layer boards have gotten, I don’t see any upside in dealing with the limitations of a two-layer PCB and the work required to assure adequate power and ground distribution.  Aside from the power/ground matter, a four-layer board can be smaller and denser, things which enhance AC performance and in some cases, actually reduce the board cost—smaller PCBs tend to be cheaper.

All of my POC units have been four-layer and I have strictly used the PLCC-44 version of the 65C816.  The DIP40 version takes up too much room, adds too much inductance to the circuits and is potentially a victim of ground bounce due to the long bond wires needed to connect the die to the pins.

All valid reasons to go 4-layer, but once a design is simplified down to 100mmX100mm, 2-layer becomes easy to design, cheaper and faster to produce. Since 2017 when I became interested in retro computers, I cannot think of any my pcb designs bigger than 100mmX100mm. There were few among them that were marginal and needed additional ground wires bodges to achieve stable operation, but vast majority of them worked just fine as 2-layer boards. I very much welcome the option of affordable 4-layer technology, but I don’t exercise that option too often.
Bill