6502.org

14c) is just a NAND gate with push/pull output,
sensing if the CPU wants to read/write the TOD MSB.

So I had integrated it into 14b).
;---

14b) TOD control

When the TOD LSB is written with high_active register write control signal W_TOD_LSB,
the "TOD count enable" RS flipflop is set at the start of the next PHI2 cycle,
what enables TOD counting with low_active signal TOD_CEN#
when high_active signal TOD_DET1 from "5b) TOD pad" signals
that there was a rising edge at the TOD pad.

When the CPU writes the TOD MSB, or when RES is active,
the "TOD count enable" RS flipflop (buit from two NOR gates) is cleared,
what disables TOD counting.
;
Note:
This means after RES was active, you would have to write TOD LSB to enable TOD counting.

"Writing TOD MSB" means:
LOW_active write enable signal WE# is active, //generated in "2) CS#, R/W#"
High_active select signal SEL_$A is active, //generated in "6) address decoder"
CRB7 control register B Bit is 0.

;...

When the CPU reads TOD MSB, the "TOD read sample/hold" RS flipflop
(built from two NOR gates) is set, and TOD_RHOLD goes active,
freezing the TOD read latches.

When the CPU reads TOD LSB with high_active register read control signal R_TOD_LSB,
or when RES is active, the "TOD read sample hold" RS flipflop is cleared,
and TOD_RSAMPLE goes active, making the TOD read latches transparent again.

"Reading TOD MSB" means:
LOW_active read enable signal RD# is active, //generated in "2) CS#, R/W#"
High_active select signal SEL_$A is active, //generated in "6) address decoder"
CRB7 control register B Bit is 0.

;...

Short form:
TOD MSB write > disable TOD counting
TOD LSB write > enable TOD counting //you have to do that after RES was active
TOD MSB read > freeze TOD read latches
TOD LSB read > make TOD read latches transparent again.

14 efg) TOD counter carry, and TOD counter control

That part looks a bit confusing in the silicon.

Note: the TOD counter Bit cells operate with the PHI20 clock.
PHI20 is HIGH at PHI2, in every fourth PHI2 cycle.
Means that TOD is clocked with PHI2/4.

I think that the designers intentionally did it this way
because the delay of the carry chain was too much
for running the counters at PHI2 speed...

;...
TOD counter (plus read latches plus ALARM registeres plus comparator)
breaks into six blocks, 4 Bit each.
Every block has its own (low_active) carry input,
its high active count clock, and its high active clear.

We could assume, that the 8520 TOD binary counter is based
on the 8521 BCD TOD counter.
Because in a BCD counter, using 4 Bit blocks this way really makes sense,
like when clearing a 4 Bit block after it had counted up to 9.

For simplifying things, let's take a look at the control logic for
the TOD counter Bits 20..23.

We have "sort of" a parallel lookahead carry mechanism:
When the next lower 4 Bit counter is cleared with TOD_CLR_16..19, this means:
the counter for Bit 16..19 is $F, counting for Bit 16..19 is enabled,
and the counter for Bit 20..23 is supposed to increment
(when the counter for Bit 16..19 rolls over to $0).

TOD_CLR_16..19 goes through an inverter, into a transparent latch clocked
with TOD_CNT_20..23 (same clock as for latches in counter Bit 20..23),
the output of that transparent latch is the low_active carry input
for counter Bit 20.
For inhibiting the carry input, the transparent latch is set when:
Bit 20..23 counter is cleared with TOD_CLR_20..23,
or when the CPU writes the counter Bits with W_TOD_MSB at PHI2.
//when loading or clearing the counter, do not count.

TOD_CLR_20..23 becomes active when RES is active,
or when timer Bits 20..23 are $F while TOD_CLR16..19 is active,
sampled at PHI20 by a transparent latch which is reset
when W_TOD_MSB is active.
//when loading the counter, don't clear it.

So the carry lookahead mechanism technically could be interpreted
as a chain of AND gates, where the TOD_CLR_* signals ripples through,
and 4 counter Bits go into every AND gate.

What complicates things:
When having "lump of logic" in the silicon between the 4 Bit counter blocks,
logic for generating the control signals of one 4 Bit counter block
is in the "lumps of logic" at both sides of said 4 Bit counter Block.


Technically, from the logic design point of view what's between the counter blocks
could be interpreted like this:

Edit: logic between counter Bit 11 and counter Bit 12 is different, sorry, see 14h).
;...

A the West end of the 4 Bit MSB counter block,
we have this litte lump of logic:
It's a bit smaller, because we don't need to generate control signals
for the next higher counter Block... because there is none.

;---

14d) TOD counter Bit 0 carry input generation

Same concept as above.
It's a bit smaller, because we don't need to check for an overflow
on the next lower 4 Bit counter Block while counting is enabled...
because there is none.

;===

14h) TOD counter Bit 12 input carry generation

Edit: dang.
The lump of logic between TOD Bit 11 and TOD Bit 12 is slightly different,
and somehow I had missed that.

Basically, we have a transparent latch controlled by PHI1,
followed by another transparent latch controlled by PHI2,
inserted into the carry chain between TOD counter Bits 11 and 12.

14g) TOD INT

Note: the TOD counter Bit cells operate with the PHI20 clock.
PHI20 is HIGH at PHI2, in every fourth PHI2 cycle.
Means that TOD is clocked with PHI2/4.

High_active signal ALARM_EQ is generated by a 24 input NOR gate,
which is distributed among all of the TOD comparator cells
(comparing the TOD counter Bits with the ALARM register Bits).
The pullup resistor (FET) of this NOR gate is integral part of 14g).

If the values in the TOD counter Bits match the values
in the ALARM register Bits, ALARM_EQ is HIGH.

ALARM_EQ is sampled by a transparent latch at PHI20,
then by another transparent latch at PHI1,
then goes into a rising edge detector.

When a rising edge is detected, high_active signal TOD_INT
goes active for one PHI2 cycle,
what sets the ALARM interrupt flag.

;...

That's all for now.
8521 is next. //HMOS-II implementation of the 6526

Thanks Dieter/ttlworks for creating something meaningful out of the vectorized pictures...

Wow, an incredible amount of work - well done, and thanks for making it all public.

I know I always say the same but... what else can I say?

This is amazing. The amount of work, effort, and knowledge put into this, is priceless.

Can't say "Thank you" enough times but..

Thank you!

Many many thanks for that great work!

@all:
Thanks for the appreciation.
Those chip dissections are very labour intensive.