G-Pascal compiler and on-board assembler for Ben Eater's PC

[plasmo]

I believe Ben Eater's configuration can run up to 24MHz and therefore G-Pascal can be accelerated accordingly. How to do 24MHz without major hardware/software surgery is the question.

I believe the weak link is EEPROM. Yes, wait state can be added for EEPROM access but that also slow down the whole system, so here is a proposal:
Have fast 64K RAM enabled for the entire 64K memory space but RAM's output enable is asserted only at lower half of the memory space. EEPROM occupies the upper 32K with wait state inserted for 24MHz operation. EEPROM's output enable is asserted at power up while RAM's output enable in the upper 32K memory space is disabled. A small bootstrap routine in EEPROM is executed at powerup that copies EEPROM to itself (must use EEPROM that's not affected by writing to self such as W27C512, SST39SF010). This operation writes EEPROM contents to the shadow RAM. After self-write is done, the bootstrap routine set a flip flop that disable EEPROM output enable and enable RAM output enable and we are now running in zero-wait fast RAM.

Thoughts?

[BruceRMcF]

For that use, If using a 74xx163 counter circuit for the clock, you could run the "normal mode" high bit straight from the latch to the counter (P0 for /2, P1 for /3), and just set it high in the part of the startup/coldstart code that comes after copying the ROM andturning off ROM select.

I can see that as a way to run a board based on a W65C02 or W65816 board at 16MHz, although starting at 5.33MHz. The WDC are reportedly able to handle it, even if there was not the market segment to justify WDC getting them retested for 16MHz labelling. Which 6502 are you expecting to run at 24MHz?

[Nick Gammon]

plasmo wrote:

The 4-line LCD display worked even at 12MHz; I noticed it needs local echoback and use line feed instead of carriage return.

It is gratifying that someone else got it to work. Did you try the assembler?

I mention the need to use local echo here here.

As for linefeeds, I'm used to Linux these days. In any case Windows sends carriage-return/linefeed and I just ignore the carriage-returns.

There may be issues with the 4-line LCD. I assumed that people had the one on Ben's board, and I'm not sure how well the addressing goes past the second line. Perhaps you can report any issues you have.

[Nick Gammon]

plasmo wrote:

After self-write is done, the bootstrap routine set a flip flop that disable EEPROM output enable and enable RAM output enable and we are now running in zero-wait fast RAM.

Thoughts?

Interesting idea. I already suggested a small change that disables writing to the EEPROM.

I don't have a 64 KB RAM, any suggestions for an appropriate one?

[Martin A]

Nick Gammon wrote:

I don't have a 64 KB RAM, any suggestions for an appropriate one?

Any 128k ram with A16 tied to ground (or or the supply)

[plasmo]

There are a number of fast 64K RAM in skinny DIP format as described in this post. Or ground one of the address line as suggested by Martin A.

I'm thinking of overclocking the standard 14MHz W65C02 to 24MHz Enough people had done this successfully that I'm pretty comfortable with the overclocking approach.
Bill

[BigDumbDinosaur]

BruceRMcF wrote:

The WDC are reportedly able to handle it, even if there was not the market segment to justify WDC getting them retested for 16MHz labelling.

WDC qualifies production at 20 MHz, i.e., production parts must perform at that clock rate to be considered good product. All currently-shipping parts are made with 0.6µ geometry dice and will easily run beyond 20 MHz if powered at 5 volts. We have had reports of the WDC 65C02 being cranked up to the 30 MHz range—highly unlikely such a thing would be successful with the older 65C02s.

My POC V1.2 unit, which is 100 percent discrete logic, can run at 20 MHz with timing headroom to spare. POC V1.3, the unit I am currently running, is also discrete logic and is stable at 16 MHz. The “ceiling” for that unit is around 18 MHz due to bank latching prop delay through the logic. In both units, ROM and I/O are wait-stated using high-phase clock stretching.

[BigEd]

> WDC qualifies production at 20 MHz, i.e., production parts must perform at that clock rate to be considered good product

Worth noting, I think, that this is testing, not characterisation. As you say, with a full power supply voltage and a reasonable operating temperature, a device will normally perform better than specification. But there's a reason why we operate with a margin relative to test - both industry and hobbyists do it - and that 20MHz is a figure from which one would expect to back off.

It's also worth noting - and most of us know this well - at increasing speeds, the performance of peripherals and glue logic become ever more important. To run a system at 20MHz demands much faster glue than to run at 14MHz. (Not to mention solid power distribution and bypass.)

[plasmo]

I ran an experiment with faster RAM (25nS 128KB CY7C109) and one wait state for flash. I added a serial port in CPLD so I can communicate with 6502 as I increase the CPU clock. I also patched in a small program to talk to the CPLD serial port and a command to transfer control to G-Pascal program.

At 24MHz I can talk to 6502 via CPLD serial port but G-Pascal serial port and LCD display are not functioning.
At 18.4MHz G-Pascal serial port and LCD display are functioning but not at 20.3MHz.

My conclusion is the VIA can not be overclocked above 18MHz but if the VIA functions are replaced by CPLD, 24MHz operation is still possible so the notion of copying flash into RAM and operating in RAM is still viable. Executing in RAM has the advantage of uploading new software to test it out before burning into flash.
Bill

[BigDumbDinosaur]

BigEd wrote:

Worth noting, I think, that this is testing, not characterisation.

Correct. It’s in the same vein as proof-testing a boiler at a pressure higher than its designed rating. Testing proves the boiler’s integrity (or lack thereof) but doesn't imply that it’s okay to operate it beyond its maximum rated working pressure.

I should also clarify that my above statement about testing production parts at 20 MHz applies to microprocessors, not peripherals. I don’t know for a fact that WDC tests the 65C21, 65C22 and 65C51 at 20 MHz. As always, YMMV.

Quote:

It's also worth noting - and most of us know this well - at increasing speeds, the performance of peripherals and glue logic become ever more important. To run a system at 20MHz demands much faster glue than to run at 14MHz. (Not to mention solid power distribution and bypass.)

Yep! We have topics on wait-stating and construction methods that anyone intent on pushing the clock limits should read.

plasmo wrote:

At 24MHz I can talk to 6502 via CPLD serial port but G-Pascal serial port and LCD display are not functioning.
At 18.4MHz G-Pascal serial port and LCD display are functioning but not at 20.3MHz.

My conclusion is the VIA can not be overclocked above 18MHz

Since current WDC VIAs are produced to 0.6µ geometry, I see no reason why one of them shouldn’t be able to run as fast an MPU. Is it possible other circuit factors are limiting the maximum speed? You could try wait-stating, but doing that with clock stretching will cause the VIA’s timer drift unless it is done in the right way (as Jeff reminded me ).

[Dr Jefyll]

BigDumbDinosaur wrote:

You could try wait-stating, but doing that with clock stretching will cause the VIA’s timer drift.

The following post features a clock stretcher that allows no-drift VIA timer operation. I would've thought you'd remember this circuit, BDD!

RDY vs CLOCK STRETCHING. Includes 2 very simple circuits.

[BigDumbDinosaur]

Dr Jefyll wrote:

BigDumbDinosaur wrote:

You could try wait-stating, but doing that with clock stretching will cause the VIA’s timer drift.

The following post features a clock stretcher that allows no-drift VIA timer operation. I would've thought you'd remember this circuit, BDD!

RDY vs CLOCK STRETCHING. Includes 2 very simple circuits.

Yeah...I recall it now but for some reason, didn't recall it at the time of my post. This old age cr*p is for the birds!

Or, as my wife claims, my head is so full of bits and bytes all the available memory has been used up.

[BillG]

BigDumbDinosaur wrote:

This old age cr*p is for the birds!

Or, as my wife claims, my head is so full of bits and bytes all the available memory has been used up.

My problem is fragmentation...

[plasmo]

BigDumbDinosaur wrote:

Since current WDC VIAs are produced to 0.6µ geometry, I see no reason why one of them shouldn’t be able to run as fast an MPU. Is it possible other circuit factors are limiting the maximum speed? You could try wait-stating, but doing that with clock stretching will cause the VIA’s timer drift unless it is done in the right way (as Jeff reminded me ).

Good call. I added a wait state and added another ground return to the VIA prototype board. Now the VIA will respond with correct sign on message most of the time but it won't respond correctly to serial input and the LCD display is flaky. I'm so far past the rated frequency that signal returns and signal loads can easily affect its operation.

So it is note worthy that Ben Eater's original design can be sped up to 12MHz with faster flash (such as W27C512) and RAM. Adding wait state logic and more solid pc board design potentially can bring it to 24MHz operation.
Bill

[Nick Gammon]

I got my breadboard system to run at 5 MHz but not 8 MHz. I strongly suspect the speed of the EEPROM is the limiting factor there.