65020

Topics relating to PALs, CPLDs, FPGAs, and other PLDs used for the support or creation of 65-family processors, both hardware and HDL.
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AndrewP
Posts: 368
Joined: 30 Aug 2021
Location: South Africa

Re: 65020

Post by AndrewP »

John West wrote:
There's no offset register, because there are no non-indexed addressing modes (except for JMP and JSR, which are obsolete with the extensions to the branch instructions). The 6502's zero page and absolute non-indexed modes have been re-interpreted as indexed, but with a default index register that's always zero.
I think I'm understanding you but just to be sure the final effective address of the Indexed modes are:

Indexed
Indexed.png
Indexed.png (4.56 KiB) Viewed 1636 times
Indexed Indirect
Indexed Indirect.png
Indexed Indirect.png (5.41 KiB) Viewed 1636 times
Indirect Indexed
Indirect Indexed.png
Indirect Indexed.png (4.82 KiB) Viewed 1636 times
John West
Posts: 383
Joined: 03 Sep 2002

Re: 65020

Post by John West »

AndrewP wrote:
I think I'm understanding you but just to be sure the final effective address of the Indexed modes are:
That's exactly right.

I haven't used the indirect modes in real code yet; just for testing that they work. They're useful on the 6502 because they're the only way to have a variable address that can point to anywhere. Now that I can put the address in a register, 16-bit-address + register is the only mode I use most of the time. (a16,X) and (a16), Y are only there for compatibility.

The indirect branches, however, are useful. Sometimes you need a jump table.
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