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/*
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* *
* W65C816S PROOF OF CONCEPT SINGLE-BOARD COMPUTER *
* *
* =============================================================================== *
* *
* Copyright (c)2021 by BCS Technology Limited. All rights reserved. *
* *
* Permission is hereby granted to use, copy, modify and distribute this software, *
* provided this copyright notice remains unaltered in the source code and proper *
* attribution is given. Redistribution, in any form, must be at no charge to the *
* end user. This code or any part thereof, including any derivation, MAY NOT be *
* incorporated into any package intended for sale unless written permission to do *
* so has been granted by the copyright holder. *
* ------------------------------------------------------------------------------- *
* THERE IS NO WARRANTY OF ANY KIND WITH THIS SOFTWARE. *
* *
* While it is believed that all code will perform as intended, the user assumes *
* all risk in connection with the incorporation of this software into any system. *
* *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * *
* VERSION HISTORY *
* * * * * * * * * *
Ver Rev Date Revision
--------------------------------------------------------------------------------
0.1.0 2021/06/28 Original version.
--------------------------------------------------------------------------------
*/
Name logic;
PartNo C106280001;
Date 2021/06/28;
Revision 0.1.0;
Designer BDD;
Company BCS Technology Limited;
Assembly POC V2.0;
Location U6;
Device f1504ispplcc44;
property atmel {cascade_logic on };
property atmel {err_file logic.err};
property atmel {fast_inlatch on };
property atmel {fold off };
property atmel {foldback_logic on };
property atmel {logic_doubling off };
property atmel {optimize on };
property atmel {output_fast off };
property atmel {pin_keep off };
property atmel {preassign keep };
property atmel {security off };
property atmel {soft_buffer on };
property atmel {xor_synthesis on };
/*
==============================================
MACHINE ARCHITECTURE IMPLEMENTED IN THIS LOGIC
==============================================
+--------------------------+ $01FFFF
| |
| |
| |
| Extended RAM (64 KB) |
| |
| |
| |
+--------------------------+ $010000
| |
| ROM (12 KB) |
| |
+--------------------------+ $00D000
| |
| SYSRAM (3.25 KB) |
| |
+--------------------------+ $00C300
| |
| HMU (0.25 KB) |
| |
+--------------------------+ $00C200
| |
| IODEV (0.5 KB) |
| |
+--------------------------+ $00C000
| |
| |
| BASRAM (48 KB) |
| |
| |
+--------------------------+ $000000
1 KB = 1024 bytes
---------------------------------
| I/O MAP (10 bits of decoding) |
---------------------------------
+--------------------+ $00C200
| |
| RESERVED |
| |
+--------------------+ $00C1C0
| |
| XIO6 | Expansion Chip Select
| |
+--------------------+ $00C180
| |
| XIO5 | Expansion Chip Select
| |
+--------------------+ $00C140
| |
| XIO4 | Expansion Chip Select
| |
+--------------------+ $00C100
| |
| XIO3 | Expansion Chip Select
| |
+--------------------+ $00C0C0
| |
| XIO2 | vQUART Channel IRQs
| |
+--------------------+ $00C080
| |
| XIO1 | DUART #2 (channels C & D)
| |
+--------------------+ $00C040
| |
| XIO0 | DUART #1 (channels A & B)
| |
+--------------------+ $00C000
Signal Type Function
=============================================================================*/
pin 33 = A6; /* input address line */
pin 34 = A7; /* input address line */
pin 21 = A8; /* input address line */
pin 24 = A9; /* input address line */
pin 25 = A10; /* input address line */
pin 26 = A11; /* input address line */
pin 27 = A12; /* input address line */
pin 28 = A13; /* input address line */
pin 29 = A14; /* input address line */
pin 31 = A15; /* input address line */
pin 5 = A16; /* output address line */
pin 39 = D0; /* input unbuffered data line */
pin 36 = DB0; /* input buffered data line */
pin 43 = PHI1; /* input system clock (phase 1) */
pin 2 = PHI2; /* input system clock (phase 2) */
pin 6 = !RAM; /* output RAM chip select */
pin 19 = !RD; /* output read data */
pin 1 = RESB; /* input system reset */
pin 18 = !ROM; /* output ROM chip select */
pin 44 = RWB; /* input MPU read/write */
pin 41 = VDA; /* input valid data address */
pin 40 = VPA; /* input valid program address */
pin 20 = !WD; /* output write data */
pin 4 = !WSE; /* output clock stretch control */
pin [8,9,17,11,12,14,16] = ![XIO0..6]; /* output I/O chip selects */
/*
=========================
BURIED LOGIC DECLARATIONS
=========================
*/
pinnode = extram; /* extended address latch */
pinnode = hmu0; /* hardware management latch */
pinnode = hmusel; /* 1 = HMU selected */
pinnode = iosel; /* 1 = I/O device selected */
pinnode = romsel; /* 1 = ROM selected */
pinnode = vab; /* 1 = valid address present */
/*
==================
FIELD DECLARATIONS
==================
*/
field addr = [A15..A6]; /* effective address LSW */
/*
==================
INTERMEDIATE LOGIC
==================
*/
hmu0.AR = !RESB;
extram.LE = PHI1;
extram.L = D0;
hmusel = extram:0 & addr:['h'C20x];
iosel = extram:0 & addr:['h'C0xx..C1Fx];
romsel = extram:0 & addr:['h'D0xx..FFxx] & !hmu0 & RWB;
/*
--- A write to ROM goes to RAM at the same address.
*/
vab = (VDA # VPA) & RESB;
/*
======
INPUTS
======
*/
hmu0.LE = hmusel & !RWB & PHI2 & vab;
hmu0.L = hmusel & !RWB & PHI2 & vab & DB0;
/*
=======
OUTPUTS
=======
*/
A16 = extram & RESB;
DB0.OE = hmusel & RWB & PHI2 & vab;
DB0 = hmusel & RWB & PHI2 & vab & hmu0;
RD = RWB & PHI2 & vab;
WD = !RWB & PHI2 & vab;
WSE = iosel # romsel & vab;
RAM = !(hmusel # iosel # romsel) & vab;
ROM = romsel & vab;
XIO0 = iosel & addr:['h'x00x] & vab;
XIO1 = iosel & addr:['h'x04x] & vab;
XIO2 = iosel & addr:['h'x08x] & vab;
XIO3 = iosel & addr:['h'x0Cx] & vab;
XIO4 = iosel & addr:['h'x10x] & vab;
XIO5 = iosel & addr:['h'x14x] & vab;
XIO6 = iosel & addr:['h'x18x] & vab;
/*
--- $00C1C0 - $00C1FF reserved for future expansion.
*/
/* * * * * E N D O F F I L E * * * * */
Code: Select all
pin 43 = PHI1; /* input system clock (phase 1) */
pin 2 = PHI2; /* input system clock (phase 2) */
Code: Select all
pin 43 = PHI1; /* input system clock (phase 1) */
pin 2 = PHI2; /* input system clock (phase 2) */
The board is electrically correct but the footprint I used for the 'AC245 transceiver was wrong. It has the right number of lands but is the wrong package width. Below is the incorrect PCB layout. The mistake is with U4, which is located at the southwest corner of the 65C816 socket.
