Test harness for identifying fake 6502s

[Chromatix]

Yes, I was cursing the JEDEC committee, who were responsible for standardising memory device pinouts, several times today. But actually, getting the right lines to the right pins wasn't so hard - it was getting them from there onwards, to the 6522 and the UART socket, that gave me fits. That's what I meant by putting the devices in a different order, as the 6522 and the UART socket are relatively easy to wire directly adjacent to the 6502.

[Chromatix]

Well, it seems I couldn't leave it alone until tomorrow. So now I have a longer but slimmer and overall smaller board - just under 200x100mm - on which the main bus runs almost straight from one end to the other, and the memory devices are on the opposite side of the CPU socket from everything else. Some of the other signals were still quite a bear to route, but this time I didn't need to intrude on the power planes at all, and the layout is much more satisfying.

I also added a power switch, since pulling out and re-inserting the jack is likely to get very old relative to operating a ZIF socket.

[Chromatix]

So, yesterday I made some minor improvements to the PCB layout, and called it v1.02. It has mounting holes to attach nylon feet, a wire or two that were bizarrely routed were fixed, and clearances to insert chip-pullers and fingers were improved where appropriate:

But then I realised that a really big improvement could be had if I put the left-hand side of the 6522 clear of the main bus, as that would massively simplify routing the various signals between the I/O ports and the sampling hardware, and thus reduce the number of vias. So that's what I did today with v1.03, which is not so much a "spot the difference" as "spot the similarities". I was able to keep a few clusters of components the same, except for moving them around, and thus save the time needed to realign and rewire them. The board is also now about 20mm shorter, which is a nice bonus.

[BigEd]

An interesting evolution - and shows the benefit in sleeping on a "finished" design before shipping it off to manufacture.

[Chromatix]

Indeed. Here's the back of the v1.03 board, which shows more of the critical routing:

In my case, actually manufacturing anything is on hold until I have enough spare cash for all the bits at once. In the meantime, I can work on the software, and on other hardware projects that I can then roll into a single, larger, more efficient parts buy.

For example, there's that "UART Card" socket next to the VIA. Technically, I can plug in anything that'll fit into a 16-byte address space, but also I can reuse such cards on other things I build with the same socket on them. So I can not only work on an actual UART card (probably very simple relative to the m/board), but more complex things like a keyboard, or a sound generator, or even a video card…

[Chromatix]

And now v1.04 is in progress. Partly motivated by noticing, purely by chance, that the 74HCT00 and '85 were not connected to the power rails.

KiCad assigns the power rails of such multi-unit chips to a separate and distinct unit, so as to keep the actual logic diagram clear. This is fine. The documentation then strongly implies that the power rails are automatically connected to nodes carrying the VCC and GND flags, if you don't explicitly specify otherwise.

But apparently not. And furthermore, it does not warn about these hidden, disconnected pins in the ERC, even though it does warn about visible pins that are disconnected and not flagged as being intentionally so. And that could have been a €50 error, had I not happened to notice that some pins on a chip I was rerouting carried a pin number but not a net name, and where is the VCC and GND on this thing?

[tingo]

You have noticed that the DRC / ERC windows in KiCad have two tabs?

[Chromatix]

Yes, and neither one of them reports a missing unit from a multi-unit IC.