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Posted: **Thu Mar 19, 2015 9:08 pm**

BigDumbDinosaur wrote:

It is recommended that a device's output-enable also be gated by Ø2, as no member of the 6502 family reads the data bus when Ø2 is low. In the case of the 65C816, devices MUST NOT be output-enabled during Ø2 low, as that is when the '816 is driving the bank bits on to D0-D7. This requirement may be met by gating write-enables with Ø2 or by using a bus transceiver (e.g., a '245) to isolate the data bus during Ø2 low. Failure to do so will likely cause bus contention and interfere with the 65C816's ability to emit the bank bit pattern.

I just thought of a problem with just using the bus transceiver and not gating /WE by PHI2 to guard against invalid writes. While the address isn't stable and/or RWB is ready first, RAM may just take whatever value is held on the data bus due to bus capacitance. This is regardless of the data transceiver being in Hi-Z state.

GARTHWILSON wrote:

I wouldn't worry about that part though. The write data isn't guaranteed to be valid anyway until tMDS after the rise of phase 2, tMDS being 30ns or more, depending on the column of speed and voltage in the table. As long as you're not writing to a wrong address, you'll do fine as long as the data is correct for the set-up time of the device (RAM or I/O IC) before the fall of phase 2 (for 65xx I/O ICs) or the device's CS\ or WR\ is taken false (for RAM or non-65xx I/O ICs).

Something to keep in mind is that not all I/O ICs have a CLK input- especially a 65xx CLK

. So it's possible to write to invalid addresses for those ICs which just try to "write the results as fast as possible" like RAM as opposed to waiting for a clock transition.

At least that's what I gleamed from this post (i.e. you don't have to worry about the write data being invalid for IO ICs because the CLK will ensure only valid data is written).

In any case, after reading the 65816 multiplexed bus topic in full, I think it's probably safe to just use a 245 and not gate reads using PHI2; when the 245 is set for a processor read, there will be propagation delay before the data value reaches the other side and starts corrupting the bank address being held to satisfy the 373's hold time. I don't think contention will ever reach the I/O/ROM/RAM side of the 245 during a read because of the way the buffers of the 245 are designed (HiZ for the direction that is not asserted). The '816 takes care to ensure writes don't cause contention.

Posted: **Thu Mar 19, 2015 10:18 pm**

Quote:

GARTHWILSON wrote:

I wouldn't worry about that part though. The write data isn't guaranteed to be valid anyway until tMDS after the rise of phase 2, tMDS being 30ns or more, depending on the column of speed and voltage in the table. As long as you're not writing to a wrong address, you'll do fine as long as the data is correct for the set-up time of the device (RAM or I/O IC) before the fall of phase 2 (for 65xx I/O ICs) or the device's CS\ or WR\ is taken false (for RAM or non-65xx I/O ICs).

Something to keep in mind is that not all I/O ICs have a CLK input- especially a 65xx CLK

. So it's possible to write to invalid addresses for those ICs which just try to "write the results as fast as possible" like RAM as opposed to waiting for a clock transition.

Hence my comment about "RAM or non-65xx I/O ICs." For those I/O ICs that don't have a phase-2 input, you'll gate WR\ with phase 2, so that either way, the write is not started until after the address is valid and stable, and the write is ended when (or a few ns after) phase 2 falls. Doing it this way, you will never write to an invalid address.

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