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Re: Issue with Indirect Addressing
Posted: Wed Feb 22, 2017 9:33 pm
by BigDumbDinosaur
Hey Jeff,
This is the NAND gate I used.
The slowness of the above circuit is due to the fact that the series transistors can only sink the output, not source it. You are depending on the 4.7K resistor to drive the output high, which means the RC time-constant of whatever is hooked up to the output will affect rise time and set a limit on how fast the circuit can change state.
Early on in the application of the transistor to digital logic, RTL (resistor-transistor logic) was developed, but soon abandoned, for reasons that you now know. TTL (transistor-transistor logic) was developed to improve switching speeds and to positively drive the output in both directions, leading to the development of the 74-series logic devices during the 1960s.
Re: Issue with Indirect Addressing
Posted: Wed Feb 22, 2017 11:27 pm
by GARTHWILSON
To add to what BDD said, suppose you have 20pF of capacitance for the 4.7K to charge up. 20pF x 4.7K makes for a 94ns time constant for the rise time! (The time constant is the amount of time it takes for the voltage to go (1-1/e) times the voltage change it will make given an infinite amount of time, meaning approximately 63% of the way to its final voltage, or 3.16V out of 5V.) One thing that would help is to replace the resistor with a current mirror. Take a look at NXP's BCM62B (Thanks Dr Jefyll for alerting me to that), or go to their website and search for "PNP double transistor" (which doesn't seem to be working for me right now). The benefit there is that you can set it for some amount of current, say 5mA, and the current will not diminish significantly until the voltage is pulled up well past a valid logic 1. (The resistor's pull-up current OTOH is proportional to the voltage across it which keeps dropping as the voltage rises.)
A related thing also slowing the transistor down is that there's another RC time constant formed by the input resistors and the transistors' base capacitances, including Miller effect. You can speed that up by putting a 10 or 20pF capacitor across each 10K resistor.
Yet another (and Dr Jefyll alluded to it) is transistor saturation. If you let them get saturated, it takes them longer to turn off. The "S" in "74LS__" basically refers to Schottky diodes put across transistors from collector to base so they turn on and shunt out the base current if the collector gets more than about a quarter of a volt below the base.
Re: Issue with Indirect Addressing
Posted: Thu Feb 23, 2017 12:09 am
by Dr Jefyll
This is the NAND gate I used.
oops -- right. I'm used to seeing
FET transistors connected in series (as is the case internally with MOS and CMOS gates), but I tend to forget it works for bipolar transistors, too. BTW, ChaseHQ85, if you like you can attach images to your post. There's no need to use imgur / whatever.
replace the resistor with a current mirror. Take a look at NXP's
BCM62B
From my notes, here's the example circuit which introduced me to the NXP part. Annotations added. See the entire original page
here.
See also
Chapter 11 - The Current Mirror on wiki.analog.com.
Yet another (and Dr Jefyll alluded to it) is transistor saturation.
Yup, I was prompted by BDD's mention of it.
Re: Issue with Indirect Addressing
Posted: Fri Feb 24, 2017 2:12 am
by ChaseHQ85
Hello again, ChaseHQ85. I'm glad to see that you found your problem. I'm providing an untested re-write of your source, in the hopes of showing you a different way of attacking the specific task you posted. I think that I understood what you were doing with your code, with the exception of your mention of the number "2820" in your comments.
When it is possible to do so, it can be of benefit to fill from higher to lower addresses on the 65xx, especially if the fill area is not an integer multiple of 256, and this is the technique I have employed here. The accumulator and Y register don't have to be initialized inside the loops, because they already have the "correct" value when the loop-backs occur. Not only is the static instruction count lower, but the nested loops execute far fewer instructions, with the net result being a more efficient system.
Code: Select all
PROCESSOR 6502
;-------------------------------------------------
;-------------DANI-I-SYSTEM-ROM-------------------
;-------------------------------------------------
;-------------EQUATES-----------------------------
VRAM: EQU $8000
VRAM_H: EQU $80
VRAM_L: EQU $00
VRAM_CMD: EQU VRAM + $F00
VRAM_CHARSLOC: EQU VRAM + $F10
VRAM_CHARSBUF: EQU VRAM + $F20
;-------------EO-EQUATES--------------------------
ORG $C000
RESET:
LDX #$FF ; Initialize the Stack Pointer
TXS ; Transfer X to Stack
SETUP_BLANKCHAR:
LDA #$00 ; Store Null in Accu
LDX #$07 ; Set X to 7
LOOP_BLANKSTORE:
STA VRAM_CHARSBUF,X ; Store Accu into VRAM_CHARSBUF+X
DEX ; (filling high to low is more efficient)
BPL LOOP_BLANKSTORE
STA VRAM_CHARSLOC ; Set the Character Store Location
LDA #$01 ; Set the Character Store Command
STA VRAM_CMD
CHECK_CMDCOMPLETE:
LDA VRAM_CMD ; Check VRAM_CMD to see if VGA picked up char
BNE CHECK_CMDCOMPLETE ; Keep checking until it resets to 00
BLANKOUT_START:
LDA #VRAM_L ; Load Low Byte of VRAM address
STA $05 ; Store it in Zero Page 5
LDY #$B0 ; Last page is only partially filled
LDA #$00 ; Set Accu To 0 (fill byte)
LDX #VRAM_H+4 ; Init X to last VRAM page number
LOOP_BL_OUTER:
STX $06 ; Store it in Zero Page 6
LOOP_BL_INNER:
DEY ; (filling high to low is more efficient)
STA ($05),Y ; Store the fill byte
BNE LOOP_BL_INNER ; ... down to the bottom of the page
DEX ; Prepare to fill next-lower page
CPX #VRAM_H ; Is X < VRAM_H?
BCS LOOP_BL_OUTER ; No: fill the next page
LOOP_DONE:
JMP LOOP_DONE ; Done: "halt" in an infinite loop
VECTORS:
ORG $FFFA ; 6502 Starts reading its vectors here
.word LOOP_DONE ; NMI
.word RESET ; RESET
.word LOOP_DONE ; BRK
END
If I messed up anywhere, please let me know, and I'll revise.
Mike B.
Hey Mike,
Quick question to make sure i understand fully what's happening. Wouldn't i need to make the only partially filled page start at B1 instead of B0 because of the DEY prior to the store?
Thanks!
Re: Issue with Indirect Addressing
Posted: Fri Feb 24, 2017 4:54 am
by barrym95838
I don't have a memory map of your set-up, but I saw you mention that your video display RAM occupies 1200 ($04B0) bytes, and starts at address $8000. If that is true, then the first byte is at $8000 and the 1200th byte is at $84AF, and my code should perform as advertised, in roughly 58% of the time yours takes to complete, due to the smaller inner loop. You still didn't explain what the "2820" meant in your source comments, so I could be misunderstanding something.
Mike B.