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Re: huge speedup with 65C02 I/O mapped into zero-page
Posted: Sun Mar 02, 2014 1:09 am
by Dr Jefyll
How about one of these little guys, Jeff?
I've used stuff like that but it's rare to find one I like. For the 6-pin I admit it works out quite nicely, so that's good to mention -- thanks. I guess my reservations apply more to the larger adapters, which typically...
- hog PCB space, and
- make no special accommodation for the power supply traces
It has occurred to me to submit improved designs to a local manufacturer of these boards, or to just make my own. But in the meanwhile I usually just do without. And nothing'll beat the density of one of my Hacker Specials!
-- Jeff
Re: huge speedup with 65C02 I/O mapped into zero-page
Posted: Sun Mar 02, 2014 1:41 am
by ElEctric_EyE
Am I missing something here? Or do you guys need some serious help?!
CPLD! FPGA!!
Re: huge speedup with 65C02 I/O mapped into zero-page
Posted: Sun Mar 02, 2014 2:01 am
by Dr Jefyll
I don't mind being teased, Sam.
There's a certain fascination with these hard-wiring challenges, and it
can get perverse. But if you look back about a dozen posts you'll see the drift is programmable-logic alternatives.
BTW I've been using programmable logic since about 1980. A bipolar PROM can really make a lot of jelly-bean logic go away.
Re: huge speedup with 65C02 I/O mapped into zero-page
Posted: Sun Mar 02, 2014 2:40 am
by barrym95838
Am I missing something here? Or do you guys need some serious help?!
CPLD! FPGA!!
Chillax, bro!
We're not trying to build a daily driver here, just tinkering around with a pile of nuts and bolts, trying to sculpt something retro-cool. I'm here to learn and be entertained, not to change the world.
Mike
Re: huge speedup with 65C02 I/O mapped into zero-page
Posted: Sun Mar 02, 2014 6:37 am
by BigDumbDinosaur
A bipolar PROM can really make a lot of jelly-bean logic go away.
Yep, poor man's PLA.
The prototype of the Lt. Kernal hard drive subsystem used an EPROM in the host adapter for glue logic. Not real speedy but it did work.
Re: major speedup with 65C02 I/O mapped into zero-page
Posted: Tue Jul 01, 2014 9:15 pm
by Rob Finch
With a softcore 6502 it would be possible to define a second page of 'zero page' just for I/O. Using up some of the available opcode space IN and OUT instructions could be defined to use the second zero page page. The instructions would have implied address bits like zero page instructions, but the page could be $D0xx for instance.
Re: major speedup with 65C02 I/O mapped into zero-page
Posted: Sat Feb 28, 2015 10:33 am
by djmips
I like your thinking. I also like the idea of having multiple zp banks with some of them I/O and RAM. When you talk about the vintage 6502 designs it came to mind that the C64 6510 had a couple of I/O registers at $00 and $01. Another more striking example is the Atari 2600 which mapped all of it's display I/O registers in zero page and this was really crucial as display operations could use every cycle you could find.