Interfacing external RAM to a Xilinx FPGA using Verilog

[Arlet]

You'll need two read registers, one for channel 1 and another for channel 2, and then something like:

Code: Select all

always @(posedge clk)
	read_data1 <=  ch1_valid_1 ? ram_d : 0;

[ElEctric_EyE]

Ok, Thanks! I have something finished and everything passes. I'll try it out.

I 've attached the version I'm trying. I know it's probably hard to look at, although I have properly formatted it in notepad as a .txt file. But do you see any glaring errors?

[ElEctric_EyE]

No luck yet. The RTL didn't look right, so I made 1 change to the last attached file.

Working on it...

[Arlet]

Keep in mind that there will be a delay when you start reading (a burst of) data. The _rd_next signals indicate that the address has been copied, and that you can now change it for the next word (if you want to read more). At that time, the data isn't valid until the data_valid signal is asserted. This means for instance that you can't just hook up a CPU core to the SRAM controller and expect it to work. Depending on the current state, it could take one or more cycles, and you would have to delay the CPU by playing with the RDY input.

[ElEctric_EyE]

Yes, it's time I checked out your machine in ISim.

[ElEctric_EyE]

The SRWEn appears to be 1 cycle late. It's not inline with SRD and SRCS.

Changing

Code: Select all

always @(posedge clk)
	SRWEn = < ~(next == WRITE1);

to

Code: Select all

assign SRWEn = !(next == WRITE1);

seems better in simulation.

[ElEctric_EyE]

It is better! More red in the randomness, since I am still trying to write (1024x768=65536x12) red pixels.

Time for more Sims and to find out when to halt the CPU now. Thanks for the lead!

[ElEctric_EyE]

The ram is rated @133MHz and the cpu & RAM is being run @70MHz. Why should the cpu be halted when the RAM is almost 2x as fast?

[Arlet]

You are right. My experience was from using a 100 MHz CPU and 10 ns RAM. Of course, if you lower the clock rate, your time from valid address -> valid data may be less than a clock cycle, which avoids the need for the extra wait state I have.

Still, you'll need to look at what you want to do when going from a read cycle to a write cycle. If you don't have any delay in between, there's going to be a period where both devices are driving the bus. And also, when the SRAM controller is in a VGA read state, there will be a delay as well.

[ElEctric_EyE]

I think what I'm going to have to do is back off the speed and start working at 15MHz with 320x200 resolution with this board. This is the lowest frequency I was able to display on my flatscreen LCD monitor. I'm not having much luck at 70MHz. I can tell the cpu is running which is a good thing, but data integrity for the displayed video is not there.

[Arlet]

You could also run some dedicated tests. First write to SRAM (really slowly) a known pattern, so you know what is in there. Then only focus on a simple read operation looping the addresses, and see if you get the correct data back.