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I wouldn't count LS as a very good choice, they don't have
much drive relatively speaking. Don't you have any HC (or
other CMOS)?

LS might be better than nothing but you could do better.
Find a CMOS bus driver.

BDD suggested using SN74ABT245 drivers, which i bought and i will use them on my new cpu board, and they are also s twice fast as the ls.

Hello,
when using some fast logic as 74ABT series, is good to terminate a bus (and very near to connector) with a 74s1051 (12-bit schottky barrier diode) or 74S1053 (16-bit schottky barrier diode). This solution work better than passive termination (series resistor, or parallel resistive partition). Shottky diodes absorbe line rerflection, not draw power and not longer the rise time.
Anyway, is ever best to terminate a bus, also when using LS/ALS/HCT line buffer.

Fast signals should not been driven to hard. Ring and overshooting are almost guaranteed. Blocking this with schottky barrier diode is a solution but it has in it's own some risks and requirements (like the requirement of good VCC bypassing. I have made better experience with AC than with the ABT. And as typically only very few signals are really "high-speed" I use passive termination on only these ones and the good Oscilloscope of my brother to check.

The "fast signals" are an unavoidable byproduct of using silicon with single-digit nanosecond performance. The effects of cumulative propagation delay can sabotage a system that relies on a lot of gates, so the use of 74ABT logic may be necessary to achieve satisfactory performance at high Ø2 clock rates. For example, latching the bank address of a 65C816 is a timing-critical operation that cannot be met with slower logic as the Ø2 rate approaches the MPU's design maximum. My timing analysis has suggested that 74AC will barely manage such an operation at 12.5 MHz. Considering that the '816 has an official maximum rating of 14 MHz and will run at 20 MHz, it's either going to be 74ABT logic or a PLD capable of 10ns or less pin-to-pin propagation time.

Incidentally, there are no "risks" associated with the use of Schottky suppression—referring to Vcc bypassing as a "risk" seems odd, given that good circuit design should be liberal with the use of bypass capacitors. At worse, a little more board real estate gets taken up, which can be addressed to some extent by use of SOIC packages.

Also incidentally, the exceptionally strong drive strength of 74ABT logic (sourcing 32ma and sinking 64ma) makes for a "stiff" output that can counteract ringing to some extent. If the circuit doesn't use long leads that meander about then ringing will be modest. Ringing problems are more a result of physical construction than anything else, and will occur even with slower logic in some cases.

Yes and no. By fast signals a merely meant the signals that are fast and need to be in sync over the whole system and must not have spikes that could be interpreted as additional transitions. The decoding of the bank address of a 65C816 is a completely different story in my opinion. Unfortunately WDC has chosen this way and at the same time the bank address would be the first stable signals because you use it to select between RAM, ROM(if you really need it) and IO. I never make a bus with these signals. I keep them close to the CPU and only the top-level decoder and the (S)RAM ever get to see them, in fact there is only a PLD and Data-Pins of the RAM and a bidirectional buffer connected to it.

The last paragraph in Dr. Johnson's reply is telling:

• In slower applications, like SCSI, diode terminations are great, because (1) the signals are intentionally slowed down to meet radiated emissions requirements, so the diodes are naturally faster than the signals, (2) we can afford to build fancy clamping-voltage generators at Vcc-Vf(diode) and Gnd+Vf(diode), and (3) we can specify receivers with tight V(IH), V(IL) margins that are tolerant of the lingering residual reflections.
  

"...slower applications, like SCSI..." is the key phrase. The current parallel SCSI standard is ultra-320, which is a theoretical bus speed of 320MB/second, 16 times the maximum speed at which a 65C816 can be run. SCSI buses since the days of fast-SCSI 20 use active terminators to deal with bus reflections on cables of as much as three meters length. At 20MHz, a Schottky barrier diode has a reverse recovery time that is only 16 percent of the machine cycle time of 50ns. So an array of these would be effective on an '816's address and data buses, which usually doesn't stretch more than a few inches. That said...
This is one of those topics where there seems to be almost as many opinions as people to express them. I daresay that in our designs we're not running things fast enough for transmission line effects to be a major problem.
NXP (Phillips) quotes maximum rise and fall time on 74ABT outputs at 2.5ns at 5 volts.

It took me a long time to find the date on the article I referenced: Jul '98. At that time, according to the Wikipedia article on SCSI, the clock rate was limited to 10MHz, which might explain where he was coming from. 2003 apparently brought much higher clock rates, and DDR. I seem to remember reading there somewhere too that each wire is monodirectional, as is the case with SPI, which would make it easier to get good perform at high clock rates. Is that correct?
If average reverse recovery time for the 16-bit 74S1053 is 8ns, it won't absorb the overshoot of a <2.5ns rise time, will it? My understanding on exactly what reverse recovery means is kind of foggy.

BTW, it looks like the 4Mx8 SRAM module's longest line (which is an address line) is about 3.4" from the tip of the connector pin to the end of the trace. These can be stood up very close together, so using more than one module does not increase the maximum trace length by more than about 0.4" per additional module.

Wikipedia is not exactly correct (not unusual). In 1990, ANSI updated the SCSI standard (X3.131-1990) to 10 MB/second in synchronous mode, but then continued to work on it for a number of technical and political reasons. The result was the 1996 SCSI-2 revision (X3.270-1996) which defined "fast-20 SCSI", meaning the bus could be clocked at 20 MHz in synchronous mode. The 16 bit bus, which had been previously introduced, could transfer data at 40MB/second.

Double-transition clocking was introduced to SCSI c. 1997, which progressed to ultra-160 and ultra-320, the latter being the fastest parallel bus implementation.
All connections are potentially bi-directional. I say "potentially" because any device on the SCSI bus can be an initiator.
Use of an edge connection scheme, like that of the memory modules used in PCs would have significantly shortened the maximum trace length. It's interesting to note that from inception, the PCI bus was clocked at 33 MHz, using edge connectors.

No. All data signals (nine including parity) are bi-directional. Any device on the bus can initiate a transaction and during the arbitration phase of selection, all devices assert a single data line to indicate their SCSI ID. As the SCSI bus is a daisy chain, data can be "flowing" in either direction. Implied is that both ends of the bus must be terminated, since a signal source could be at either end or somewhere in between. It's not at all like most parallel bus arrangements, including IEEE-488.

This is something I know little about, but would like to see discussed in this context.

I presume some of the higher-speed "ribbon" cables today occur in the flexible plastic interface feeding high-res laptop & tablet displays. Have most of these moved to serial protocols due to all the aforementioned issues?