Posted: Wed Sep 07, 2011 11:16 am
Lee...
There will be errors in this ... Ive been correcting it all night
To rotate the wrist requires two steppers that are rotated equally in opposite directions.. And to flex the wrist the same two steppers have to run in the same direction.. I don't think they implemented combination moves but I could be wrong, (by stepping one motor at a different count than the other would cause a flex and rotate at the same time)..
You probably picked this info up already from the partial manual on the ctrl-c website but I reiterate just in case it was missed..
The Teaching Pendant consisting 14 buttons probably monitored by 4 X 4 matrix polling routine,, But I could be wrong will have to disassemble the pendant to trace it out,, And the 5 LED's Seem to each have its own outputs,, And an additional user defined 5 TTL outputs on Plug P17.. NOTE the pendant has nothing but the 14 switches in it,, And the 5 LED's with current limiting resistors.. That plugs into the P15 Header.. I have yet to map the pendant..
There are leftover Hex Inverters on the 74LS14 Clock/Reset circuit that are used in address decoding.. One pair double inverts phi-2 for delay line of 30 to 44ns,, And the other inverts A15 Address to CS\ on the 2732A Eprom..
74LS251 handles 9 inputs, 7 User Inputs plus one combined Pendant & Gripper tension micro-switch input paired to a single input.. My guess the E-Stop button is the one paired with the gripper...
Keyboard is 14 keys minus 1 are probably on a 4X4 Matrix so (4 in) (4 out) Plus (5 out) for the LED's And another (5 out) on P17 for User outputs,, Total 18
______________________________________
P17 user I/O ?? The 74LS251 output is tri-state and toggles D7, But I can't see where it's output is being limited to the read cycle only...
-----------------------------------------------------
pins 2 & 15 P17 GND and Pin 1 = +5
pin 15 = I4 < pin 10 P17 User Optional Input
pin 14 = I5 < pin 12 P17 User Optional Input
pin 13 = I6 < pin 14 P17 User Optional Input
pin 12 = I7 < pin 16 P17 User Optional Input
pin 01 = I3 < pin 08 P17 User Optional Input
pin 02 = I2 < pin 06 P17 User Optional Input
pin 03 = I1 < pin 04 P17 User Optional Input
pin 04 = I0 < pin 12 P15 Pendant & P16 Gripper SW
Pin 05 = Z\ > NC or not found
pin 06 = Z > pin 26 on CPU & VIA - D7
pin 07 = E1 < pin 09 74LS138 Addressing
pin 09 = S2 < pin 11 cpu - A2
pin 10 = S1 < pin 10 cpu - A1
pin 11 = S0 < pin 09 cpu - A0
_______________________________________
R6502A CPU Pins with * have pull-up resistor
------------------------------------------------------
pin 4 = IRQ *
pin 6 = NMi *
_______________________________________
VIA 6522 Pins with * have pull-up resistor
-------------------------------------------------------
pin 35 RS3 < A3 cpu
pin 36 RS2 < A2 cpu
pin 37 RS1 < A1 cpu
pin 38 RS0 < A0 cpu
pin 24 CS1 < pin 23 A13 cpu
pin 23 CS2 < pin 25 A15 cpu
pin 40 CA1 - single pin header E4 NC
pin 39 CA2 - single pin header E5 NC
pin 18 CB1 - single pin header E7 NC
pin 19 CB2 > pin 03 & 04 ACIA U13 & U15 RX & TX Clock
pin 25 Phi-2 < pin 12 LS14 delayed Phi-2 30 to 44ns
pin 34 Res < pin 40 cpu = Reset
pin 22 R/W <pin 34 cpu = R/W
pin 21 IRQ >pin 06 cpu = NMI *
pin 02 PA0 < pin 01 P15 pendant *
pin 03 PA1 < pin 02 P15 pendant *
pin 04 PA2 < pin 03 P15 pendant *
pin 05 PA3 < pin 04 P15 pendant *
pin 06 PA4 < pin 05 P15 pendant *
pin 07 PA5 < pin 06 P15 pendant *
pin 08 PA6 < pin 07 P15 pendant *
pin 09 PA7 - pin NC or not found *
pin 10 PB0 < pin Baud Dip Switch 1 *
pin 11 PB1 < pin Baud Dip Switch 2 *
pin 12 PB2 < pin Baud Dip Switch 3 *
pin 13 PB3 < pin Baud Dip Switch 4 *
pin 14 PB4 > pin 10 P15 pendant
pin 15 PB5 > pin 11 P15 pendant
pin 16 PB6 - pin NC or not found
pin 17 PB7 - single pin header E6 NC
______________________________________
68B50 ACIA Addressing & Clock U13 & U15 Are the same except for pin 09 = CS2\
-----------------------------------------------------
pin 07 = IRQ > pin 04 cpu
pin 08 = CS0 < pin 24 cpu
pin 09 = CS2\------ ACIA U13 pin 09 < pin 22 = A12 cpu ------ ACIA U15 pin 09 < pin 20 = A11 cpu
pin 10 = CS1 < pin 08 74LS14
pin 11 = RST < pin 09 cpu
pin 13 = R/W < pin 34 cpu
pin 14 = ENA < pin 12 74LS14 Delayed phi-2
pin 03 & 04 = RX & TX clock < pin 19 = CB2 on U19 VIA
_______________________________________
74LS14 is the standard Clock & Reset circuit
------------------------------------------------------
Pins 1-2-3-4 Crystal & Clock (Crystal & Caps now removed and pin 1 driven by a 1.8432mhz crystal oscillator)
Pins 5-6 Power on Reset circuit
pin 09 < pin 25 A15 6502
pin 08 > pin 20 on 28 pin eprom socket which is pin 18 on the 2732 CE\
pin 11 < pin 39 6502 Phi-2 out
Pin 10 > pin 13 input LS14
pin 12 > pin 25 VIA -- pin 06 = E3 74LS138 -- pin14 = Ena ACIA U13 & U15 ((Delayed Phi-2 30 to 44ns))
______________________________________
74LS138 address decoding.. seems their using Phi2 as part of the decoding
-----------------------------------------------------
pin 01 = A0 < A10 cpu
pin 02 = A1 < A11 cpu
pin 03 = A2 < A12 cpu
pin 04 = E1 < A14 cpu
pin 05 = E2 < A15 cpu
pin 06 = E3 < pin 12 74LS14 Delayed Phi-2
pin 15 = 0 > pin 08 U16 & U17 first 1k of ram
pin 14 = 1 > pin 08 for piggybacked second 1k of ram from the E1 single tie point
pin 13 = 2 > pin 09 74LS174 U12 Base U11 and 1/2 Shoulder U07
pin 12 = 3 > pin 09 74LS174 U05 Elbow U04 and 1/2 Shoulder U07
pin 11 = 4 > pin 09 74LS174 U09 R-Wrist U10 and 1/2 L-Wrist U06
pin 10 = 5 > pin 09 74LS174 U02 Gripper U03 and 1/2 L-Wrist U06
pin 09 = 6 > pin 07 74LS251 U23
pin 07 = 7 > pin 14 74LS259 U22
______________________________________
74LS259 Addressable Latch
-----------------------------------------------------
pin 01 = A1 < pin 09 cpu A0
pin 02 = A2 < pin 10 cpu A1
pin 03 = A3 < pin 11 cpu A2
pin 04 = Q0 > pin 14 of P15 pendant
pin 05 = Q1 > pin 13 of P17 user
pin 06 = Q2 > pin 11 of P17 user
pin 07 = Q3 > pin 09 of P17 user
pin 09 = Q4 > pin 07 of P17 user
pin 10 = Q5 > pin 05 of P17 user
pin 11 = Q6 > pin 09 of P15 pendant
pin 12 = Q7 > pin 13 of P15 pendant
pin 13 = D < pin 33 cpu D0
pin 14 = E\ < pin 07 74LS138 Addressing
pin 15 = C\ < pin 40 cpu Reset
______________________________________
UDN5707A Each of the 4 NAND gates have their inputs paired to a single single 74LS174 output
-----------------------------------------------------
There will be errors in this ... Ive been correcting it all night
To rotate the wrist requires two steppers that are rotated equally in opposite directions.. And to flex the wrist the same two steppers have to run in the same direction.. I don't think they implemented combination moves but I could be wrong, (by stepping one motor at a different count than the other would cause a flex and rotate at the same time)..
You probably picked this info up already from the partial manual on the ctrl-c website but I reiterate just in case it was missed..
The Teaching Pendant consisting 14 buttons probably monitored by 4 X 4 matrix polling routine,, But I could be wrong will have to disassemble the pendant to trace it out,, And the 5 LED's Seem to each have its own outputs,, And an additional user defined 5 TTL outputs on Plug P17.. NOTE the pendant has nothing but the 14 switches in it,, And the 5 LED's with current limiting resistors.. That plugs into the P15 Header.. I have yet to map the pendant..
There are leftover Hex Inverters on the 74LS14 Clock/Reset circuit that are used in address decoding.. One pair double inverts phi-2 for delay line of 30 to 44ns,, And the other inverts A15 Address to CS\ on the 2732A Eprom..
74LS251 handles 9 inputs, 7 User Inputs plus one combined Pendant & Gripper tension micro-switch input paired to a single input.. My guess the E-Stop button is the one paired with the gripper...
Keyboard is 14 keys minus 1 are probably on a 4X4 Matrix so (4 in) (4 out) Plus (5 out) for the LED's And another (5 out) on P17 for User outputs,, Total 18
______________________________________
P17 user I/O ?? The 74LS251 output is tri-state and toggles D7, But I can't see where it's output is being limited to the read cycle only...
-----------------------------------------------------
pins 2 & 15 P17 GND and Pin 1 = +5
pin 15 = I4 < pin 10 P17 User Optional Input
pin 14 = I5 < pin 12 P17 User Optional Input
pin 13 = I6 < pin 14 P17 User Optional Input
pin 12 = I7 < pin 16 P17 User Optional Input
pin 01 = I3 < pin 08 P17 User Optional Input
pin 02 = I2 < pin 06 P17 User Optional Input
pin 03 = I1 < pin 04 P17 User Optional Input
pin 04 = I0 < pin 12 P15 Pendant & P16 Gripper SW
Pin 05 = Z\ > NC or not found
pin 06 = Z > pin 26 on CPU & VIA - D7
pin 07 = E1 < pin 09 74LS138 Addressing
pin 09 = S2 < pin 11 cpu - A2
pin 10 = S1 < pin 10 cpu - A1
pin 11 = S0 < pin 09 cpu - A0
_______________________________________
R6502A CPU Pins with * have pull-up resistor
------------------------------------------------------
pin 4 = IRQ *
pin 6 = NMi *
_______________________________________
VIA 6522 Pins with * have pull-up resistor
-------------------------------------------------------
pin 35 RS3 < A3 cpu
pin 36 RS2 < A2 cpu
pin 37 RS1 < A1 cpu
pin 38 RS0 < A0 cpu
pin 24 CS1 < pin 23 A13 cpu
pin 23 CS2 < pin 25 A15 cpu
pin 40 CA1 - single pin header E4 NC
pin 39 CA2 - single pin header E5 NC
pin 18 CB1 - single pin header E7 NC
pin 19 CB2 > pin 03 & 04 ACIA U13 & U15 RX & TX Clock
pin 25 Phi-2 < pin 12 LS14 delayed Phi-2 30 to 44ns
pin 34 Res < pin 40 cpu = Reset
pin 22 R/W <pin 34 cpu = R/W
pin 21 IRQ >pin 06 cpu = NMI *
pin 02 PA0 < pin 01 P15 pendant *
pin 03 PA1 < pin 02 P15 pendant *
pin 04 PA2 < pin 03 P15 pendant *
pin 05 PA3 < pin 04 P15 pendant *
pin 06 PA4 < pin 05 P15 pendant *
pin 07 PA5 < pin 06 P15 pendant *
pin 08 PA6 < pin 07 P15 pendant *
pin 09 PA7 - pin NC or not found *
pin 10 PB0 < pin Baud Dip Switch 1 *
pin 11 PB1 < pin Baud Dip Switch 2 *
pin 12 PB2 < pin Baud Dip Switch 3 *
pin 13 PB3 < pin Baud Dip Switch 4 *
pin 14 PB4 > pin 10 P15 pendant
pin 15 PB5 > pin 11 P15 pendant
pin 16 PB6 - pin NC or not found
pin 17 PB7 - single pin header E6 NC
______________________________________
68B50 ACIA Addressing & Clock U13 & U15 Are the same except for pin 09 = CS2\
-----------------------------------------------------
pin 07 = IRQ > pin 04 cpu
pin 08 = CS0 < pin 24 cpu
pin 09 = CS2\------ ACIA U13 pin 09 < pin 22 = A12 cpu ------ ACIA U15 pin 09 < pin 20 = A11 cpu
pin 10 = CS1 < pin 08 74LS14
pin 11 = RST < pin 09 cpu
pin 13 = R/W < pin 34 cpu
pin 14 = ENA < pin 12 74LS14 Delayed phi-2
pin 03 & 04 = RX & TX clock < pin 19 = CB2 on U19 VIA
_______________________________________
74LS14 is the standard Clock & Reset circuit
------------------------------------------------------
Pins 1-2-3-4 Crystal & Clock (Crystal & Caps now removed and pin 1 driven by a 1.8432mhz crystal oscillator)
Pins 5-6 Power on Reset circuit
pin 09 < pin 25 A15 6502
pin 08 > pin 20 on 28 pin eprom socket which is pin 18 on the 2732 CE\
pin 11 < pin 39 6502 Phi-2 out
Pin 10 > pin 13 input LS14
pin 12 > pin 25 VIA -- pin 06 = E3 74LS138 -- pin14 = Ena ACIA U13 & U15 ((Delayed Phi-2 30 to 44ns))
______________________________________
74LS138 address decoding.. seems their using Phi2 as part of the decoding
-----------------------------------------------------
pin 01 = A0 < A10 cpu
pin 02 = A1 < A11 cpu
pin 03 = A2 < A12 cpu
pin 04 = E1 < A14 cpu
pin 05 = E2 < A15 cpu
pin 06 = E3 < pin 12 74LS14 Delayed Phi-2
pin 15 = 0 > pin 08 U16 & U17 first 1k of ram
pin 14 = 1 > pin 08 for piggybacked second 1k of ram from the E1 single tie point
pin 13 = 2 > pin 09 74LS174 U12 Base U11 and 1/2 Shoulder U07
pin 12 = 3 > pin 09 74LS174 U05 Elbow U04 and 1/2 Shoulder U07
pin 11 = 4 > pin 09 74LS174 U09 R-Wrist U10 and 1/2 L-Wrist U06
pin 10 = 5 > pin 09 74LS174 U02 Gripper U03 and 1/2 L-Wrist U06
pin 09 = 6 > pin 07 74LS251 U23
pin 07 = 7 > pin 14 74LS259 U22
______________________________________
74LS259 Addressable Latch
-----------------------------------------------------
pin 01 = A1 < pin 09 cpu A0
pin 02 = A2 < pin 10 cpu A1
pin 03 = A3 < pin 11 cpu A2
pin 04 = Q0 > pin 14 of P15 pendant
pin 05 = Q1 > pin 13 of P17 user
pin 06 = Q2 > pin 11 of P17 user
pin 07 = Q3 > pin 09 of P17 user
pin 09 = Q4 > pin 07 of P17 user
pin 10 = Q5 > pin 05 of P17 user
pin 11 = Q6 > pin 09 of P15 pendant
pin 12 = Q7 > pin 13 of P15 pendant
pin 13 = D < pin 33 cpu D0
pin 14 = E\ < pin 07 74LS138 Addressing
pin 15 = C\ < pin 40 cpu Reset
______________________________________
UDN5707A Each of the 4 NAND gates have their inputs paired to a single single 74LS174 output
-----------------------------------------------------