6551 vs 6850 vs 8250 vs ?

PaulF · Post by **PaulF** » Tue Sep 06, 2011 9:21 am

When using Motorola 68xx chips with the 6502, the E line should be connected directly to the 6502's phase 2 output. Although this line is called Enable, it is not a chip select line, it is a timing line with the same function as the 65xx series phase2 line.

It is called Enable because it is used to indicate that data should be enabled onto the data bus by a devices' 3-state drivers when it is active.

BigDumbDinosaur · Post by **BigDumbDinosaur** » Tue Sep 06, 2011 1:56 pm

PaulF wrote:

When using Motorola 68xx chips with the 6502, the E line should be connected directly to the 6502's phase 2 output. Although this line is called Enable, it is not a chip select line, it is a timing line with the same function as the 65xx series phase2 line.

It is called Enable because it is used to indicate that data should be enabled onto the data bus by a devices' 3-state drivers when it is active.

Told you my memory was hazy.

Dajgoro · Post by **Dajgoro** » Sun Oct 02, 2011 5:00 pm

When i connect my 6850 with the rs232, can i leave the receive clock running all the time, or it must be synced with the rs232 data?

leeeeee · Post by **leeeeee** » Sun Oct 02, 2011 5:46 pm

The Rx clock should be running all the time.

GARTHWILSON · Post by **GARTHWILSON** » Sun Oct 02, 2011 7:30 pm

Yes. Again, RS-232 is asynchronous.

Dajgoro · Post by **Dajgoro** » Sun Oct 02, 2011 11:50 pm

I know that rs232 is usually associated with uart, anyway what is the difference between acia and uart?

leeeeee · Post by **leeeeee** » Sun Oct 02, 2011 11:59 pm

An ACIA only implements a subset of character lengths, parity, start and stop bit and break options. A UART should do them all.

GARTHWILSON · Post by **GARTHWILSON** » Mon Oct 03, 2011 1:56 am

I've never heard of a distinction. The 6551 ACIA does do the whole set AFAIK:

5, 6, 7, or 8 data bits
1, 1.5, or 2 stop bits
odd, even, mark, space, or no parity
full duplex
programmable echo mode
transmit data, continuous stop, or continuous break
15 programmable baud rates, + external 16x clock source like for MIDI which is 31.25kbps

Is there anything else?

leeeeee · Post by **leeeeee** » Mon Oct 03, 2011 2:10 pm

All UARTs are ACIAs but not all ACIAs are UARTs.

BigDumbDinosaur · Post by **BigDumbDinosaur** » Mon Oct 03, 2011 2:54 pm

Dajgoro wrote:

I know that rs232 is usually associated with uart, anyway what is the difference between acia and uart?

None...two different terms describing the same functionality.

BillO · Post by **BillO** » Tue Oct 04, 2011 11:38 pm

A USART (like a 2651 or 16550) is the big boy in low speed communications. Both the ACIA and UART have subset functionality and are essentially the same.

BillO · Post by **BillO** » Wed Oct 05, 2011 12:01 am

GARTHWILSON wrote:

I see now in the data sheet that for the 1MHz 6850, the CS lines need to be valid at least 80ns before E rises; so yes, E would definitely have to be gated by phase 2, whereas the chip selects must not be. For the 1.5MHz part, it's 60ns min, and for the 2MHz part, it's 40ns. You could probably run phase 2 directly to the E input by itself. As long as the CS lines are not all true, it won't do anything.

Hmmm, I've hung the E input to Vcc and gated phi2 with the CS2 through a 74ls138. It seems to work fine and has for many years.

Dajgoro · Post by **Dajgoro** » Wed Oct 05, 2011 12:11 am

Since i have lots of stuff that uses serial com, i made myself a small switching circuit 4 to 1 for the acia. Do i have to switch the rts cts signals too, or can i connect them directly both from max232 to the acia(rts will need an or gate, i think)?

GARTHWILSON · Post by **GARTHWILSON** » Wed Oct 05, 2011 12:48 am

Quote:

I see now in the data sheet that for the 1MHz 6850, the CS lines need to be valid at least 80ns before E rises; so yes, E would definitely have to be gated by phase 2, whereas the chip selects must not be. For the 1.5MHz part, it's 60ns min, and for the 2MHz part, it's 40ns. You could probably run phase 2 directly to the E input by itself. As long as the CS lines are not all true, it won't do anything.

Hmmm, I've hung the E input to Vcc and gated phi2 with the CS2 through a 74ls138. It seems to work fine and has for many years.

Well, I suppose WDC is not the only company with errors in their data sheets!

BillO · Post by **BillO** » Wed Oct 05, 2011 1:31 am

You know, I never even looked at the datasheet.

I had the 6850 knocking around and saw a circuit for a UK101 work-like which I discovered in the projects section of this site that used it. While the rest of the circuit is different, I used his connection schema for the 6850 and it's clock. I figured if it worked for him it would work for me. And it did!

Over the years I have put Lee's EhBasic on it as well as OSI basic, Pittman's Tiny Basic and Micro-chess. More recently I had actually wanted to find a romable Forth to put on it as well, but ran out of steam on that. It's been a real trooper.

Just looked at the datasheet for 6850, and according to it, it should not work!