OE\ or W\ need to be low when Φ2 is high, not low.
Somehow I managed to get the phase of Φ2 backwards. Thanks for pointing that out. I'll have to go through the rest of the circuit and see if I've made the same mistake elsewhere.
Yes, I forgot some call Φ0 "Φ2 in". On the DIP, it's pin 37.
Yep, that's the one.
On the Φ2 qualification, try to do it later in the glue logic, so there aren't so many gate delays between Φ2 and the device you're enabling. Also, instead of bring Φ2 into everything, bring it in only for things that need it.
I've warmed up to this way of doing it. As I mentioned before, late qualification allows for more flexibility in selection of IO devices. The initial attraction of early qualification had to do with the FRAM stuff, but I'm thinking I need to redesign all of that anyway.
3 to 5mA would be plenty visible, and if the IC could pull it up to 4V at 5mA, then (4-1.7)V/5mA=460 ohms, and 470 is a standard value so that would work fine-- if the RST IC can pull up that much current ok.
I'll have to look into the driving power in the datasheet. Thanks.
Your ideas will keep evolving, even improving, even after you've started building, meaning you will tend to always be dissatisfied with last week's ideas that you're busy building today. They also tend to become so complex that you'll never live long enough to finish it and get anything at all going.
I'm fully aware of how that goes. I've got so many ideas bouncing around already that it's a little crazy. The other night I started a list of "IO ideas" and just kept coming up with more and more.
Been there, done that. What I've found works better, for more reasons than the newcomer would dream of, is to do a basic design that can be expanded later, but to plan on many of the features you add later to be interfaced through the I/O ICs like the 6522 instead of directly on the bus.
Despite my focus on the CPU bus at this stage, I don't actually intend to hang most of my IO directly on the bus. However, one needs a way to put the IO ICs on the bus in the first place. Therefore, you have two choices, either you have to put them on the mainboard, or you have to export the main bus. At this point the latter seems more attractive, primarily due to it's flexibility.
Also, plan to take advantage of the synchronous-serial ICs. There are thousands of them on the market, in SPI, I²C, Microwire, other 2- and 3-wire interfaces, even dumb shift registers like the 74xx165 and '595.
Oh, I am. It seems like all the interesting new chips are serial these days. Besides onboard stuff, it seems all the external interfaces (USB, SATA, PCIe), are moving to serial as well. Even CPU interconnects have gone serial in some architectures. It seems memory and UARTs are the only parallel devices left.
The 74xx164 and '595 can be connected directly to the 6522's synchronous-serial port. But even without those, you can bit-bang these interfaces very easily-- far faster and more easily than trying to bit-bang an RS-232 port.
Well, personally, I've got no interest in RS-232. (The computer I use on a regular basis doesn't have an RS-232 port.) However, I get your point about ease of interfacing.
You can even get a floating-point coprocessor with a serial interface for Pete's sake.
I know, I've though about adding one at some point. However, I'm not quite sure what I'd
do with floating point. I'd probably be more interested in one with integer multiply and divide.
Look into our
65SIB also, a very flexible, multi-purpose, multi-protocol, serial interface bus.
I've seen the 65SIB specs and I'm pretty impressed. I'm planning on putting 65SIB on an IO board.
@loop: lda (src),y — sta (dst),y — iny — bne @loop — inc src+1 — inc dst+1 — dex — bne @loop
