Sorry, I'm not completely sure how you'd validate or investigate the CPLD code - maybe looking through the detailed timing report, or comparing the high level synthesis resource tables between two runs. (In the case of synthesising to FPGA, you can get the tool to dump out a netlist of primitives, and look through that)
Just one tip which might be helpful: when I said this was a don't care situation, I meant specifically that you should tell the synthesis tool that you don't care. But I was too lazy to look up the details. It looks like the VHDL idiom is to assign X to signals when you want to tell the synthesis that it should do whatever is best:
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(others=>'X');Quote:
The way I get around this is that I assign values for all outputs. However, if I don't want to be specific with some of them and I just don't care what their outputs are, use 'X' which is for assigning all unknown or don't care values. And so the case statement must be
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when "00" => mux_out1 <= mux_in1; mux_out2 <= "0011";
when "01" => mux_out1 <= mux_in2; mux_out2 <= "0010";
when "10" => mux_out1 <= mux_in3; mux_out2 <= (others=>'X');
when "11" => mux_out1 <= mux_in4; mux_out2 <= (others=>'X');
when others =>
Ed