n00b Verilog Questions

[Arlet]

The problem remains that your input signal toggles a number of times within the delay period, which means there's no simple way to do this.

[ElEctric_EyE]

Instead of thinking of it that way, where 'countflag' is used as the flag to be monitored and delayed, maybe it's better to delay the previous signals that trigger 'countflag'.
'hstart' triggers 'countflag' positive, 'hblank' triggers 'countflag' negative. Would it make sense to delay 'hstart' & 'hblank'?

[Arlet]

I think the most natural solution is to look at incoming hsync/vsync, sync on those, and make new hstart/hblank.

[ElEctric_EyE]

I've hit a block...
Centering horizontal is not a problem. Delaying HSYNCin by 5 cycles does that well enough.
Centering vertical has been a real challenge. Delaying any one signal by the needed 11 cycles results in no visible change in vertical position. Ive tried delaying the VSYNCin, venable and vcount_done signals individually. I thought for sure I had it when I noticed venable controls the down counter and the vertical state machine, but nothing. I don't think I'm too far off the solution am I?

[Arlet]

Instead of looking at delaying signals, I think you should try to sync the state machines. So, the first board is just free running, and determines the timing, and the second and subsequent boards try to sync their state machine. Syncing can be done by halting the state machine in a certain state, and waiting until the incoming signals are at the same point, and then releasing the state machine again.

I don't understand why you have 5 and 11 cycles delay. Doesn't the delay depend on when the boards are switched on ?

[ElEctric_EyE]

Thank you for tolerating my struggles, I apologize to everyone else. This is the last thorn...

All 4 boards are sync'd, i.e. when I hit reset any any one of them all 4 pixel streams are still sync'd after initial powerup, they are just skewed.

Soon I'll post a block diagram of how I have the signals routed, and also post your vga generator I modified.

I would like to continue this discussion in the proper thread.

[ElEctric_EyE]

Another n00b question regarding Verilog and concatenation of bits using the '{}' operator.
Is it {MSb,LSb}? which I would have found more logical, but has always thrown me in a loop.
Or {LSb,MSb}? I just need confirmation. Is this really correct thinking?

[Rob Finch]

Quote:

Is it {MSb,LSb}? which I would have found more logical,

It's {MSB...LSB}. MSB on the left, LSBs to the right.

I've been following along, and I don't understand why the VSYNC signal would need significant delays. It can't be out more than a few clock cycles. Shouldn't the propagation delay in the VSYNC be about the same as the delay in the HSYNC ?

[ElEctric_EyE]

That's what I would have thought as well... Thanks Rob!
Let me finish the block diagram... My lack of understanding hinders me, but I still make progress...

What I can say is any delays I have put on any of the signals that affect VSYNC do not actually delay pixel output vertically. Which is why I've had to resort to delaying horizontally "a great many cycles" in order to align vertically. For example, in order to delay 2 pixels vertically, I have had to delay the 'hstart' signal by 2x1024 cycles.

This has worked but it is not efficient and I am puzzled why delaying a VSYNC signal differs from delaying an HSYNC signal.

[Arlet]

For vertical offset, keep in mind that you'd have to delay vsync in steps of a whole line, which is in effect "a great many cycles" if you count the pixels, but is only a small number if you count hlines.

But the question remains why you'd need such fixed offsets anyway.

[ElEctric_EyE]

Arlet wrote:

...But the question remains why you'd need such fixed offsets anyway.

I think it may have to do with how I am attempting to sync the state machines used in your vga module between successive boards.
When a positive HSYNCin or VSYNCin is detected, it resets the appropriate counters just like the hcount_ done and vcount_done signals do.

Code: Select all

...// adjust down counter. Reload when it's done.
always @(posedge clk) 
	     if ( HSYNCin | hcount_done )
				hcount <= { 1'b0, hload };...

Code: Select all

...// adjust down counter. Reload when it's done.
always @(posedge clk) 
	if( venable ) begin
	     if ( VSYNCin | vcount_done )
				vcount <= { 1'b0, vload };...

Also, when HSYNCin or VSYNCin goes active, The state machine is forced to the VIDEO state. Maybe this is wrong? But when I try to sync to any other state, I see no video.

Code: Select all

...// when down counter is done, go to next state
always @(posedge clk)
		if( hcount_done )
			case( hstate )
				VIDEO : hstate <= FRONT;
				FRONT : hstate <= SYNC;
				SYNC  : hstate <= BACK;
				BACK  : hstate <= VIDEO;
			endcase
				else if (HSYNCin) 
					hstate <= VIDEO;...

Code: Select all

...// when down counter is done, go to next state
always @(posedge clk) 
	if( venable & vcount_done ) 
			case( vstate )
				VIDEO : vstate <= FRONT;
				FRONT : vstate <= SYNC;
				SYNC  : vstate <= BACK;
				BACK  : vstate <= VIDEO;
			endcase
		else if (VSYNCin)
			vstate <= VIDEO;...

[ElEctric_EyE]

...unrelated to previous questions...

For a signal that is common to some modules, is it best to have the logic that derives that signal on the top level?
For example, if I need a display enable signal, 3 signals are needed to generate it: hstart, hblank and vblank. I could generate the display enable within it's own module and output it to other modules, or I could generate it on the top_level. What is the accepted method in Verilog?

[MichaelM]

I would place it at the level most appropriate for the functional decomposition of your system. If you have a sub-module whose function is video control, I'd put it in that module, and bring it up to the top module and distribute it from there. However, if you don't have a module whose function is video control, I'd generate the signal in the top module until such time as there's a need to create a video control module.

[ElEctric_EyE]

Michael, thanks for the pointer, what you say makes sense maybe I'm getting tunnel vision. Just FYI, Arlet's original .vga controller outputs hstart, hblank, vstart and vblank. Maybe it's a clue...
But let's say for arguments' sake that I modify that video control module to output a display enable signal:

Code: Select all

//display enable
always @(posedge clk)
	if ( hstart )
		countflag <= 1;
		else if ( hblank | vblank )
			countflag <= 0;

So it uses 3 signals and no other modules use those signals. But another module, the external RAM interface, uses the vstart signal to start the pixel counter used for the address:

Code: Select all

// pixel counters for 2MBx18 external SyncRAM
reg [9:0] X;
reg [9:0] Y;

always @(posedge clk)
	if ( vstart | X == 1023 & Y == 767 ) begin
			X <= 0;
			Y <= 0;
		end
			else if ( X == 1023 ) begin
				Y <= Y + 1;
				X <= 0;
			end
				else if ( countflag ) 
					X <= X + 1;

If the situation were reversed and 3 signals were used externally, and 1 internal would it be best to have this code present in the top module? What about 2 external and 2 internal? or will the tools just figure this stuff out?
So far in my testing I haven't noticed any change but I am chasing down a problem, so I'm 'getting my ducks in a row'. Thanks!

[Arlet]

I would probably make a separate module to fetch bitmaps from memory, and send the pixel data to the video output, so that the external RAM interface would just offer a multi-port generic memory interface, without any dependency on pixels or screen sizes.