Project: Digital Fuel Injector Pulse Width Analyzer
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ElEctric_EyE
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kc5tja wrote:
Non sequitor here: Electric_eye, how hot does the CPU get when driven at 20MHz?
It's undergoing no stress test right now though. I was just amazed it ran at all at that speed. The WDC spec's are VERY conservative. I'm sure they tested it under ALL conditions. Maybe if I lived at the equator I wouldn't get away with this speed...
Back down to 5MHz when running from SRAM ATM.
Still having problems with indirect indexed 16K copy using $00 and $01. I even tried to shorten 16K to 4K ($F000-$FFFF), i.e. bring it close to where I was having success copying $FF00-$FFFF without indirect indexed. no luck yet.
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BigDumbDinosaur
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ElEctric_EyE wrote:
kc5tja wrote:
Non sequitor here: Electric_eye, how hot does the CPU get when driven at 20MHz?
x86? We ain't got no x86. We don't NEED no stinking x86!
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ElEctric_EyE
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BigDumbDinosaur wrote:
ElEctric_EyE wrote:
kc5tja wrote:
Non sequitor here: Electric_eye, how hot does the CPU get when driven at 20MHz?
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GARTHWILSON
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ElEctric_EyE
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!
Right. Thanks. I'm done here for awhile
I don't think you'd necessarily need a fan; but maybe a larger heatsink. And, if that kind of cooling WERE needed, a cup with an icecube in it should work fine. After all, such a trick allowed the author of the C128 port of CP/M to complete his work before the Las Vegas CES show in 1984!!
Anyway, I'm glad to hear that the 20MHz operation doesn't contribute significantly to thermal concerns.
Anyway, I'm glad to hear that the 20MHz operation doesn't contribute significantly to thermal concerns.
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BigDumbDinosaur
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Fill It 'n Chill It
ElEctric_EyE wrote:
BigDumbDinosaur wrote:
ElEctric_EyE wrote:
kc5tja wrote:
Non sequitor here: Electric_eye, how hot does the CPU get when driven at 20MHz?
x86? We ain't got no x86. We don't NEED no stinking x86!
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ElEctric_EyE
- Posts: 3260
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- Location: OH, USA
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ElEctric_EyE
- Posts: 3260
- Joined: 02 Mar 2009
- Location: OH, USA
I was ready to abandon this project yet again soon after my last post here. At the time, some problems seemed insurmountable from my lone hobbyists' point of view...
Don't get me wrong, lots of good people have helped me in this forum (also Xilinx' forums) which is one of the reasons I am able to push forward with confidence. But when it comes down to making a circuit work on a piece of error laiden software (ISE 10.1), it becomes downright demoralizing if you don't know how to correct the "problem".
Andre suggested to perform "Clean Up Files". I've done this many times, but I was petrified to do this because sometimes I would just get an error with no explanation and at this point I would have to reenter the schematic from scratch.
After these past couple months of working with the Spartan 2 FPGA, I've learned to save "chapters" of progress, i.e. many different folders containing project files, each folder with new, updated modifications. Some of these would even crash and I would have to regress to a previous folder, one that could tolerate a "Clean Up Files" and continue on to create a useable JTAG file. I really felt like 1 step forward, 2 steps backwards. You can imagine how frustrating this would be! Many of us have been there more than once, during prototyping. Hobbyist or not!!
Question: Why pursue it?
Answer: I'm hardheaded, stubborn and determined. Eager to learn. And, from experience, I know Xilinx XC9572 CPLD's worked very well in ISE 11.1 in my last iteration. No issues in ISE 11.1 as in ISE 10.1. This one issue only that I've had to deal with, as mentioned in the previous paragraph.
Some advice I can give at this point: If anyone chooses ISE10.1 (you have to if using a Xilinx legacy product like the Spartan 2) for schematic input and are experiencing similar issues, I recommend this thread: ( http://forums.xilinx.com/t5/Old-ISE-Boa ... /m-p/21544 . In addition, I used the schematic file only, from the previously crashed project folder, as a copy source file into the new project. Saves me hours of work, takes less than a minute, and keeps me motivated! Some other file must be defuncting ISE. Thankfully not the schematic file.
My other piece of good news is I have the Atmel ATTiny24 programmed, including fuses, and ready to wire in (Thanks to Daryl!) for a PS2 keyboard interface. My intention is to use a very simple monitor to modify the OS in SRAM so I can quickly reprogram it to experiment with the display.I'm tired of waiting 40 seconds for each "burn" for the 512K EEPROM for a single variable change!!
Last bit of news is the most exciting for me. I have abandoned my lame 4 bit counter idea to copy EEPROM to SRAM to make the 6502 run faster from SRAM. I have also abandoned my idea to entirely copy the 512K EEPROM onto the 2M SRAM.
I have a 1 bit software programmable flip flop controlling phase 2 frequency "on the fly", using a synchronizer similar to Paul Fellingham's? creation: http://6502.org/mini-projects/clock-swi ... ching.html . But here: http://www.design-reuse.com/articles/?id=5827&print=yes to avoid metastability issues inherent inside hi speed FPGA's. Just two more flip flops, and abit more delay after the phase 2 switch which is tolerable.
Once I get it working at top speeds, the intent is to copy as needed any size, at any time, and from anywhere inside a 512Kx8 banked EEPROM to anywhere inside a 2Mx8 banked SRAM while the OS is smoothly running withOUT resetting. Software branches and jumps will still be limited to be within the window size.
Don't get me wrong, lots of good people have helped me in this forum (also Xilinx' forums) which is one of the reasons I am able to push forward with confidence. But when it comes down to making a circuit work on a piece of error laiden software (ISE 10.1), it becomes downright demoralizing if you don't know how to correct the "problem".
Andre suggested to perform "Clean Up Files". I've done this many times, but I was petrified to do this because sometimes I would just get an error with no explanation and at this point I would have to reenter the schematic from scratch.
After these past couple months of working with the Spartan 2 FPGA, I've learned to save "chapters" of progress, i.e. many different folders containing project files, each folder with new, updated modifications. Some of these would even crash and I would have to regress to a previous folder, one that could tolerate a "Clean Up Files" and continue on to create a useable JTAG file. I really felt like 1 step forward, 2 steps backwards. You can imagine how frustrating this would be! Many of us have been there more than once, during prototyping. Hobbyist or not!!
Question: Why pursue it?
Answer: I'm hardheaded, stubborn and determined. Eager to learn. And, from experience, I know Xilinx XC9572 CPLD's worked very well in ISE 11.1 in my last iteration. No issues in ISE 11.1 as in ISE 10.1. This one issue only that I've had to deal with, as mentioned in the previous paragraph.
Some advice I can give at this point: If anyone chooses ISE10.1 (you have to if using a Xilinx legacy product like the Spartan 2) for schematic input and are experiencing similar issues, I recommend this thread: ( http://forums.xilinx.com/t5/Old-ISE-Boa ... /m-p/21544 . In addition, I used the schematic file only, from the previously crashed project folder, as a copy source file into the new project. Saves me hours of work, takes less than a minute, and keeps me motivated! Some other file must be defuncting ISE. Thankfully not the schematic file.
My other piece of good news is I have the Atmel ATTiny24 programmed, including fuses, and ready to wire in (Thanks to Daryl!) for a PS2 keyboard interface. My intention is to use a very simple monitor to modify the OS in SRAM so I can quickly reprogram it to experiment with the display.I'm tired of waiting 40 seconds for each "burn" for the 512K EEPROM for a single variable change!!
Last bit of news is the most exciting for me. I have abandoned my lame 4 bit counter idea to copy EEPROM to SRAM to make the 6502 run faster from SRAM. I have also abandoned my idea to entirely copy the 512K EEPROM onto the 2M SRAM.
I have a 1 bit software programmable flip flop controlling phase 2 frequency "on the fly", using a synchronizer similar to Paul Fellingham's? creation: http://6502.org/mini-projects/clock-swi ... ching.html . But here: http://www.design-reuse.com/articles/?id=5827&print=yes to avoid metastability issues inherent inside hi speed FPGA's. Just two more flip flops, and abit more delay after the phase 2 switch which is tolerable.
Once I get it working at top speeds, the intent is to copy as needed any size, at any time, and from anywhere inside a 512Kx8 banked EEPROM to anywhere inside a 2Mx8 banked SRAM while the OS is smoothly running withOUT resetting. Software branches and jumps will still be limited to be within the window size.
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GARTHWILSON
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ElEctric_EyE
- Posts: 3260
- Joined: 02 Mar 2009
- Location: OH, USA
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ElEctric_EyE
- Posts: 3260
- Joined: 02 Mar 2009
- Location: OH, USA
kc5tja, thank you for responding. It was brought up by Dr. Jefyll a few posts ago, but...
I am unfamiliar with slowing the 6502 down this way. From what little I understand, I could force a hardware RDY state by WAI command, or send a hardware signal straight to the RDY pin?
I'm unsure how to go about this.
I am unfamiliar with slowing the 6502 down this way. From what little I understand, I could force a hardware RDY state by WAI command, or send a hardware signal straight to the RDY pin?
I'm unsure how to go about this.
If I didn't have so much on my plate now, I'd try to write up a tutorial. :/
Yes, RDY can be driven externally as well as internally. The idea for the internal drive was to let an external LED illuminate (via buffering) for diagnostic purposes (at least that's what is written in my data sheet). This is why one should use a resistor to feed RDY.
Yes, RDY can be driven externally as well as internally. The idea for the internal drive was to let an external LED illuminate (via buffering) for diagnostic purposes (at least that's what is written in my data sheet). This is why one should use a resistor to feed RDY.