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My update collided with your reply. I read through the w65c265sxb and w65c265qxb schematics again.

Both use the same reset circuit which I have added as an image above. Looking at their reset schematic the 1uf cap acts to debounce the button. I'm not sure how it compares to just using the DS1813. I'm not certain of the purpose of D5, but I'm guessing it ensures no current flows from C16 into RESB, but either to ground or back to Vcc.

The w65c265sxb has 270-ohm current limiting resistors on the serial port's rxd and dsr lines, while the w65c265qxb has no resistors and is identical to my schematic. Both are powered by the USB port, so they never have the no power scenario my board has. If I have battery power with USB connected it's basically the same as the w65c265qxb. So, I don't think it's causing my clean reset issue.

That is not a good circuit, as the push button is directly shorting out the capacitor.

Thanks BDD. I didn't like it, so it's good to hear that it's not just me.

I reviewed the ds1813 data sheet and verified my PCB against it. I think my reset circuit is correct and something else is causing the reset issue. I have a few ideas to try tomorrow.

My concern is that as you're using the DS1813, if the accidentally derived Vcc is floating around the trigger voltage for the reset circuit, it could either never reset, leaving the processor running but not formally reset, or randomly reset multiple times.

Ironically, it might well work better with the usable but not terribly good circuit shown.

Neil

You may have mentioned it a number of posts back, but I don’t recall what you are using as the power supply.  Have you determined that it will produce a well-regulated 5 volts?  As Neil notes, if VCC is sagging, the DS1813 might be running right at its trip point.

The power supply is either a 5 cell NiMH pack or a 6-volt at 1 amp wall wart fed into a LDO 5-volt regulator. I have 10uf and 100uf electrolytic capacitors on the input and output sides of the regulator. I have used similar circuits with prior 65c02 projects, and it works well.
I understand your concern. When I am powering it off the battery or wall wart, Vcc will be at 5 volts, not the 2.7 volts leaking through the protection diode. That's why I don't think it's the issue if I am careful about power up. But I agree the 2.7 volts is a problem if I plug the USB in before the battery or wall wart.

I think a more robust design for the USB interface would be similar to an I2C bus (e.g. a diode with a pull up on the port's rxd and dsr lines). That way the computer host pulls the line down without the normally high voltage leaking through. Something to add to the V2.0 design.

I did tests today with my scope on power up. I noticed that on power up sometimes PHI2 doesn't become a normal square wave. But if I hit reset again it will. This is also before the USB adaptor is connected. I have two hypotheses on the cause.

1. During reset the system's current draw might be higher than the LDO regulator and capacitors can provide. This causes Vcc to dip and the 65c265 never comes cleanly out of reset. While I have all the required decoupling capacitors. Perhaps another capacitor across Vcc and Gnd could buffer this possible higher current draw?

2. The FCLK oscillator halts and restarts during a reset, then PHI2 matches its output. I have noticed that when PHI2 doesn't become a normal square wave the oscillator isn't running. Hitting reset a few times will eventually produce a healthy oscillator and PHI2 output. This might be a symptom and not a cause, but it makes me wonder if I haven't fully resolved my oscillatophobia.

In your photo attached here
viewtopic.php?p=115103#p115103
you have an electrolytic near the power connector - it's normal, I think, to have an electrolytic near the power source, and that's a different thing from the decoupling caps near each active chip.

But is that on the incoming side? Would it be right to have such a thing upstream of the LDO, or downstream? Or both?

You would generally want a larger electrolytic (or MLCC) across the input; across the output you might also want a smaller (10n) cap to handle high frequencies that an electrolytic can't (electrolytics effectively have a lower capacitance at HF). That said, with the 11117 and similar LDO parts I usually find a 10u MLCC across the input and 1u MLCC at the output, close to the pins, does the job.

The job of the input capacitor is to smooth the incoming voltage from current spikes, and the output cap is there to keep the amplifier in the LDO stable and stop it oscillating. You do need to consult the data sheet for each and every part; they're all different.

I wonder if six volts might be too close to the lower limit for the LDO regulator, though.

Neil

Needing to press reset multiple times is troubling. I’m wondering whether there are mechanical intermittent contacts that are changed by the action of pressing reset button? Problem may have nothing to do with reset but rather the flexing of the circuit board.
Bill

My opinion is yes, it’s too close.

Interesting you mention that.  You may recall I had trouble with my POC V1.2 unit periodically going on the fritz.  The problem turned out to be a solder joint on one of the SRAM’s pins that was being flexed when I inserted a ROM into its socket.  The socket was close to the SRAM and that flexing eventually cracked the SRAM’s marginal solder joint.  Sometimes it would connect...and sometimes it wouldn’t.

Thanks for the feedback. I did some tests based on your suggestions.

First, a picture is worth 1KB words, so attached is a picture of the power supply schematic. The LDO section is similar to the datasheet, except the datasheet used either a 10uf on both sides of the regulator, or 10uF and 22uF. I used 100 uF on the output because in my previous microcontroller projects I had better luck with a larger value there.

Second, a video is worth at least 10KB words. So, here's a video showing the problem:
https://youtube.com/shorts/eYIPIO_oL6k? ... Ua2B2tRDqk

Tests and results:

1. Measure the LDO DC output and stability while using the 6-volt adapter. It was 5.02 volts. I used my scope to look for ripples, and it seemed steady.

2. Solder a 0.1 uF capacitor across the LDO output to supplement the 100 uf cap. It didn't seem to make much of a difference or improve reset behavior.

3. Briefly test the reset bug using a 12-volt adapter. It still happened.

4. After a good reset, push on the PCB in various spots (e.g near the reset button) to see if I could provoke misbehavior. No problems occurred which again confirms my impression that the board remains stable after a good reset.

Could it be that the 100µF capacitor is too large? I had a similar problem in the 80s with a home-made memory expansion for the Vic-20, where I had gone a bit overboard with the capacitors; the problem went away once I removed a large(ish) capacitor, leaving only the decoupling capacitors.

Thanks for the suggestion. To test this, I connected an external 5v supply to the XBUS header and retested. It seemed a smidge more reliable but bad resets still happened. I then connected a fully recharged 5 cell NiMH pack to the PCB power jack, it seemed more stable, but bad resets still happened randomly.

To test the hypothesis that there's a low-quality solder joint. After I had it running properly, I gently flexed and pushed on the PCB. No system instability occurred. Once running it seems perfectly stable. This problem seems limited to system initialization after a reset.

I'm wondering if the C5, C6 decoupling capacitor values are too low. The datasheet is silent about their values, so I went with the 10nF values from the w65c265qbx schematic. I used 0.1uF for C7 and C8 (from the w65c265qbx schematic) which is more typical. I consulted a chart of suggested decoupling capacitor values by system frequency and 10nF was on the low side of the range.

The good news is that when the system is running, it is stable, and I can easily use the onboard monitor. I set the date and time, although the software RTC runs fast on a 3.6864 Mhz system using the on-board monitor.

Update: I added a picture of the completed board.

I replaced C5 and C6 with 0.1 uF capacitors and retested. It's hard to tell due to the random nature of the problem, but I think it is slightly worse.
I will probably restore the 10 nF capacitors, but test with no decoupling capacitors out of curiosity.
I also have enough parts to build a second board, so I might build it as a sanity check to see if both have the same problem.