6502.org

the USB chip doesn't have any select lines, only 2 inputs for RD and WR, 8 data lines, and 2 "flags" of sorts, which are active low and connected to the 3 state buffer at the bottom left of the board.

hmm, so would it be better to leave the power lines floating instead? or just have the whole thing shut down when the power switch is off

Okay, if RD and WR are active-high, then the chip will be deselected by powering down the logic driving them. This should ensure the 8 data lines are tri-stated.

The flag lines are then the principal concern. If either of them are pulled high for any reason, that will be seen at the inputs of the tri-state buffer.

well the RD line is active low while the WR is active high.

I could just pull the RD line high to Vcc without the switch being on, to ensure it's high.
same with the tri state buffer's OE lines.

but then the question is what's with the GALs that these lines come from?

I think it would just be easier to have the whole thing shut down when the switch is off.
or alternativly just not have anything to do with power and just hold the RESET line low for as long as it's on... nah, i think powering the whole down would be the best option.

I had a look at the datasheet
https://www.ftdichip.com/Support/Docume ... FT240X.pdf
and was mildly surprised: both RD# and WR are pulses, or strobes. If I've read it right, it's the trailing edge of the low-going RD# or the high-going WR which commit the access.

ok just to make sure because i'm about to order the new batch of PCBs, when the power switch is off all Vcc connections are connected through a resistor to ground... and that shouldn't cause any problems, right?
so not even the USB chip stays active everything is disconnected from the power input (ie the USB Port's Vcc pin)
the only reason i wanted it to stay active in the first place was so that the COM Port wouldn't disappear from the Task Manager and Terminal programs, which would've been a bit helpful, but is not necessary.
Write is a simple strobe yes, it latches the data on the falling edge of the WR signal.
but RD will output the data for as long as the RD signal stays low. unless i'm reading the datasheet wrong. because T1 (RD# Active Pulse Width) only has a minimum time, not a maximum.

ok i actually found a mistake i made with the Reset line on my PCB. fixed that and now it should be ready to ship.

though i also wanted to play around with the ATF1504, but since i never worked with it i don't want it directly on my SBC...
instead i want to design and order some "smart" breakout boards. with smart meaning that all imporant pins are kina grouped together (like GND and Vcc lines) instead of it just being a straight PLCC to DIP adapter.
but i'm already running into issues with this chip, for example some of the pins don't seem to be explained anywhere, like the Global Clocks (GCLK), Global Reset? (GCLR), PD, and EO. are they optional pins? should i use a or all Global Clock pins when using the PH2 clock for decoding? etc.
another thing: it never really mentions what type of JTAG connector it uses. it just mentions the 4 signals required.
I'm almost sure it's the 10 pin JTAG type, but the pinouts i find online are kinda inconstant, they often switch the sides of the pins, but then again that shouldn't matter because i can just rotate the connector. but it would still be nice to know exactly how it should be on the PCB.
a second problem is the fact that i need a programmer, i really don't want to spend 50 bucks on an offical one unless i have to. (I'm cheap)
I checked Ebay to find some, and came across these things: LINK
20 bucks, JTAG, but it says Lattice instead of Atmel so i'm not sure...

I also thought about getting this USB Blaster, which isn't compatible with the ATF1504, but with the MAXII CPLD i also wanted to play around with. it has more IO Pins, a lot more Macrocells, and is around the same price as the ATF1504, only downside it's 3.3V logic so it requires some input voltage shifting in order to connect it to the CPU's Address/Control lines. the outputs shouldn't matter as any 5V device should see 3.3V as a logic High.

anyways besides that i've been programming around a bit with my current board since it still is a functional computer.
and my confusion about the 65c02's Flags continue as i recently got a "Get String" function complete...
aparently i don't understand the Zero flag, i thought it would be set when the output of an arithmetic/logic instruction is equal to 0. but aparently not.
I have a simple loop in my "Get String" function that checks if there is data inside the FT240X, by constantly checking the status pins of the chip.
If there is no data to read bit 1 of the byte is "1", if there is data to read that bit is "0"
here is my loop (the wrong one): my idea was the following:
This is the input data when there is no data to read: 0bxxxxxx1x (x = don't care)
so if you AND this by 0b00000010 the output should be: 0b00000010, right?
but for some reason that sets the Zero flag, so it doesn't do the BNE instruction and just continues with the rest of the function....
but why?

.

sorry for the loaded post

Your understanding of the Z flag seems correct.

Looking at your assembly code:
Is the "AND 0b00000010" assembling to the immediate AND (0x29 0x02) or the zero-page AND (0x25 0x02) or the absolute AND (0x2d 0x02 0x00)?
In Z80 assembler, it's the difference between "AND A,0b00000010" and "AND A,(0b00000010)".
6502 assembler usually looks like "AND #0b00000010" for immediate and "AND 0b00000010" for zero-page or absolute.

i converted the code from my usual Z80 style to 6502 style to make it easier to read... but i forgot some symbols...
it's an immediate value.

here the format in my Z80 style:
0x00 = Immediate
[0x00] = Zero-Page
(0x0000) = Absolute

technically i could change it to automatically use the Zero Page when the absolute address is less than 0x0100.
CustomASM is actually able of doing stuff like that, and i did do it for the Classic 6502 style, but for some reason i didn't for this one...

Also, when testing single bits in something like a status register, the BIT instruction can be helpful as it can change flags without changing the contents of the accumulator. Here's a small chunk of code from my BIOS which supports a NXP UART:

That's a bit confusing, becuase in standard 65C02 syntax, LDA ($00) loads the contents of what $0000,$0001 is pointing to. Just to be totally clear:
So what syntax do you use for indirect loads through a pointer in zero page?

As said above, that's confusing. Put that in front of a long-time 6502 assembly language programmer and they'll be scratching their head.

well that is just the standard Z80 syntax, only thing i added is the Zero page [] stuff. which as said i could technically remove with some changes to the Assembler. so you could imagine most of these with just () instead of [].
This is the reason i take my time to convert my Z80 Style code to 6502, as to not confuse you guys here.
personally i just find a lot better (because i started with the Z80) which is why i program with it at all...
ok let me explain from the start so it makes sense what i'm about to show.
1. You load an immediate byte
2. you use that byte to load 2 values from Zero page
3. you use those 2 values as absolute address to load the final value from and into the A Register.
so in total it would become this:
1. Immediate byte: LD A, *
2. used for Zero-Page: LD A, [*]
3. and finally ABS Address: LD A, ([*])

same with the X and Y offset ones, where you just add X or Y to either step 2 or 3 to get:
LD A, ([*, X])
LD ([*], Y)

I know it's kinda convoluted but it makes sense to me, it's like math where you evaluate brackets away.
same with the Jump Indirect

a regular jump is just an Immediate value, so it would be something like:
JMP 0x8000
but an Indirect jump uses the 2 immedate bytes as an Absolute Adress to load the final values from
so, following the same logic as before it would be:
JMP (0x8000)

well luckly i never really wanted to use the 65816.
I've kinda made my own version of that CPU that i can throw on an FPGA.
which can also address 16MB of Memory but unlike the 65816 it doesn't deal with banks, it just has a 24 bit Program counter and overall deals with 24 bit addresses (excetp direct page stuff of course)
and i plan on using that CPU once i fiquire out how to wire up and program FPGAs on standalone boards.

speaking of which, i kinda want to focus back on the ATF1504 stuff. i know some of you have dealt with this chip before.
so i'd like to point back to the comment above about my confusion with it. like the pins, JTAG pinout, Programmer choice, etc.
(technically the MAX II as well)

Right. But something to keep in mind is that the Z80 doesn't have indirection through a pointer in memory, so LD A,(1234h) is unequivocal.
Ok, I think that you may be using the wrong terminology here and this may be creating some of the confusion. I think you don't mean the zero page addressing mode, but the indirect addressing mode, right? I.e., you're not differentating between (in traditional syntax) LDA $22 assembling to AD 22 00 (absolute) or A5 22 (zero page), both of which are valid assemblies, both of which have the same effect, and neither of which is indirect, right?

And I am guessing that when you said "ABS address" for LD A,([nnnn]) you really meant indirect address; in your syntax the 6502 absolute addressing mode, which indicates using the contents of a memory location (with no indirection) would be LD A,(nnnn), if I'm reading it right.

You may find it useful to look at this LDA instruction reference; it shows most of the addressing modes (missing only the "(Indirect)" mode, which exists only on the JMP instruction on non-CMOS 6502s.)

Assuming that's correct, I personally think it would be a good idea always to use 6502-style #-prefix for immediate, no prefix for absolute loads from memory (whether zero page or not), and brackets of some sort for indirect, and change your assembler to do that. While introducing LDA ([$1234]) or whatever probably isn't such a big deal, Making LDA ($1234) ambiguous seems destined to lead to problems and debugging when copying code around. (Remember that, though you chose square brackets for indirection, many 6502 assemblers use parentheses instead.)
Yeah, I think you've found an inconsistency there; if instead of JMP we had a LDPC instruction, it would make sense to write LDPC #$8000.