6502.org

i guess it's a matter of suck it and see. the advantage of the fast (ok very fast) clock approach is that it could be more stable and (once you've found the right divisors) should work for different clock frequecies.

how where you hoping to introduce a delay? i can't think of any way off the top of my head that would have good stability (wrt temperature etc), but then electronics is not my strongest point...

testing 1, 1, 1, 2, 3...

Jame's post did not show up, unless you did a search on all messages posted by user. At the bottom, it showed page 2 of 1!...so I'm adding this one to see if it will appear!

Daryl

P.S. After posting this originally, James message did appear.

> how where you hoping to introduce a delay? i can't think of any way off
> the top of my head that would have good stability (wrt temperature
> etc), but then electronics is not my strongest point...

You can get ICs that are specifically programmable delay lines, with step sizes of, for example, 3ns, 5ns, etc.. One well-known manufacturer is Data Delay Devices, Inc., www.datadelay.com . I think you'll find others like Maxim and Linear Devices make them too. For a result that won't be as consistent over temperature and power supply voltage, you could experiment with something like an adjustable RC at the input of a fast Schmitt-trigger gate, like a 74AC14. Using a really fast comparator you could get better control of the hysteresis so you'd have pretty consistent, reliable results.

> Jame's post did not show up, unless you did a search on all messages
> posted by user. At the bottom, it showed page 2 of 1!...so I'm adding
> this one to see if it will appear!

I think I've had this problem before on this forum too, where the next page does not show up until the second message is added to it. It's not the only bug.

Garth

Lee,

How about we put the Mitsubishi information right on 6502.org in datasheets/parts information section? I've had a lot of requests for information on these and similar microcontrollers and I'd like to start building sections with this information.

Regards,
Mike

Firstly, apologies for resurrecting a 15 year old (at the time of writing) post...

However, I have the same issue as the OP had back then - trying to some sort of reference design for a 65c816 based SBC. Or any design, really.

I built some 6502 systems from scratch some 30 years back - today (well "now" as in +/- a few months!) I'm making another... Currently experimenting with 65c02 on a breadboard with a view to making a PCB, but thought about the 816 thing and how relatively easy it would be to drop one in-place, but other than this thread and the data sheet there's little else I can find, although Daryl Rictor does have a very nice SBC-4 page at http://sbc.rictor.org/sbc4.html

One niggle though is that I don't want to use a CPLD as I have a desire to keep it all through hole (although I'll be using a GAL or 2) - desperately trying to keep it "authentic" retro as it were. (whatever that is) however from what I can see, I shouldn't have any issues - other than that delay issue... My aim is for 8Mhz initially, any more is a bonus.

So if I do go down the 816 route (or as Garth Wilson suggests, use option-select jumpers) then it seems almost too easy. I guess the $6502 question is; has anyone else made an '818 board and is willing to share some information on it?

Thanks,

-Gordon

Hi, Gordon. No worries -- I don't think anyone minds having an old thread resurrected. As for 65816, two projects that come to mind are BDD's POC 1 and POC 2.

cheers,
Jeff

Thanks Jeff. I see POC1 is TTL-only, where POC2 used a GAL originally and now a CPLD. Daryl's SBC-3 uses a CPLD. So, POC1 might be the best example for a no-programmable-logic simple '816 computer.

Joachim Deboy's pc65816 builds might be worth a look:
https://www.pc65816.de/en/index.html
First is TTL, second uses CPLD.

Ah, that's great, thanks.

So overnight the little grey cells have been ticking over and I think the '816 is the way forwards for me here. Almost because there aren't enough 816 systems out there, however my aim is an interactive self-hosted system with a high level language compiler, monochrome graphics (320x240 composite video - already done) local storage, not relying on cross compiling, etc. I think the 816 will be a good fit for this. (And I never had an Apple //gs, but plenty of Apple ][, BBC Micro and other 6502 system experiences)

BDDs only goes up to 48K RAM though, so no extra high address line latch which is what I was really looking for. Daryl is using a CPLD in his design, so I was really just looking for some alternatives and 128KB+ I've seen the data sheet latch arrangement and will look to replicate that in a GAL - my concern is the mention above of needing a delay, presumably delaying the latching of the data bus after Ph2 goes low, at higher speeds. We'll see.

It seems it's becoming harder and harder now to build a retro style computer though - through hole stuff is becoming scarcer and scarcer, best make it now while I can! The hardest part? Video - can't get those old video chips now - well, some on ebay, but it would be just too easy to stick a Raspberry Pi0 there, but then where do you stop... My concession is using a GAL and some of the micros of the time used ULAs (about '82 onwards - BBC Micro, Spectrum, etc. and I think Apple used PALs on their later Apple //e, etc.) so I feel that's not too out of the question. (although don't get me started on Atmel vs. Lattice GALs and how useless the cheap Chinese programmers are!!!)

Anyway great that there is 15+ years of information here. Long may it continue!

Thanks.

-Gordon

For my projects, I always had used the Conitec Galep 3 programmer (plugs to LPT).
Galep 4 still has LPT, Galep 5 has USB.

Galep 3 (and later) Conitec programmers might be cheap on ebay nowaday.
But a new Galep 5 still costs an arm and a leg.

A Conitec distributor in the UK would be Equinox.

Hi Gordon,

As long as you use a transparent latch vs. a clocked register, you won't need a delay. In the 65816 datasheet, they use a 373 or 573 with an inverted PHI2 as the LE input. This is exactly how I programmed my CPLD's. I did not use a delay in my code.

The idea is that when the LE is hi (PHI2 low), the output will follow the input. So as the upper address bits are settling, so will the latch outputs, and before PHI2 goes high. When PHI2 goes high and LE goes low, the inputs are stable and get latched before the data bus pins change to the data signals. There's no need to try to clock a register at a delayed PHI2 low point.

I hope this helps. My SBC-4's CPLD was really just a large address decoder and IO buffer. There was no magic going on inside that could not be done with conventional logic.

Hope this gives you some confidence that you can build a 65816 computer with more than 64k of memory.

Daryl

I dunno why the W65C816SXB can't be used as a reference design. https://wdc65xx.com/boards/w65c816sxb-e ... nt-system/

It's an '816 with W65C22 VIA, W65C21 PIA, and W65C51 ACIA. 32K of RAM, and a 128K Flash chip (that can be mapped in 32K chunks). I think the FLASH has the monitor on it (there is no actual ROM on the board). All of the address lines are decoded on the expansion connector (which is nice). The board only maps out 64K of space, I assume if you want to go beyond (via expansion) that it's polite enough to not stomp on all of the other banks (i.e. it's actually decoding 00:XXXX vs XX:XXXX), but I don't know. (Edit: I went back and looked, and yes, it's decoding bank 0. There's big, fat NOR feeding a BNK0 signal.)

This is the schematic:
http://www.westerndesigncenter.com/wdc/ ... 816SXB.pdf

But it's a pretty basic '816, using discreet logic for decoding, and it plugs in the basic peripheral chips. There's also a monitor listing you can leverage. In fact ideally the monitor is actually designed to work with the buggy '51 chip (I think that's that one). This isn't one of the microcontrollers, it's the core CPU and other chips. It's also 8MHz, which ain't nothing.

It's not thru hole (I don't think, not sure with the sockets). But I think it solves the primary problems with talking to the CPU, especially the address decoding.

That doesn't use more than 64K of the memory space, although the flash rom is 128K it seems to be banked in 32K sections. (which is interesting in it's own right) The real thing I was after was other peoples ideas and usage of the upper 8 bit latch to expand memory > 64K, but I think I have a good handle on that now, thanks.

Address decoding and whatnot isn't much of an issue, but I've changed tact slightly due to what I plan for it as the '816 will run my applications a lot better than the c02 ever did.

Thanks,

-Gordon

I have a couple IIgs's. They are an absolute joy to use. A little pricey to upgrade, however. Just about everyone who owns one wants to overclock it and put a bunch of RAM in it. Which is really pricey. Just not my cup of tea.
I'm not sure how true that is. Warning, shameless plug....I just created one called the Potpourri6502 that's all through-hole and using newly made parts. I think we'll have through-hole parts for years to come. Just too many devices out there that need them. Of course, SMD is a great choice too. But I wouldn't go SMD just because through-hole are on the decline.

Granted, if you want FPGA and/or CPLD then yeah...through-hole is getting harder for them. Especially 5V versions. But the ATF1504/8 are still good options there. But you said no PLD's.

This is the single biggest reason it has taken me so long to build my first SBC. I never could find a video solution that I like. The closest one that I recommend is a Parallax micro-controller. It has a bunch of pro's. Such as 40 pin DIP, low part count (crystal and EEPROM), has an active and helpful community, and can drive NTSC, PAL and 64 color VGA without breaking a sweat. The con's are 3V3 only. And, it can be difficult to interface to a really fast computer. Especially 8+ MHz like you're talking.

I wished someone smarter than me would create a nice, easy VGA solution using an ATF1508 (or maybe 04 if possible) and create an easy interface for it. Upload the code as open source, etc.

I'd love to just drop one of those on my computer and have it generate primitive VGA graphics out of RAM during the half-cycle of RAM access like the Apple II did. It would be the closest thing we could get to a modern, through-hole, "somewhat cheap" solution to graphics with 6502 computers.

True; but don't let the supposed difficulty in soldering scare you off. SMT ICs with .050" lead spacing are pretty easy to do. I describe how I do it at viewtopic.php?p=48875#p48875 . Someone might be appalled that I use a big soldering iron to do it, but the picture two posts above that show the results.

I found some links to low-level VGA designs and posted them over here:
viewtopic.php?f=10&t=2054&p=63799#p63799