barnacle wrote:
but at speeds up to 2MHz with no faster testing
I'm trying to replace a dual-ported RAM with some manner of bus sharing. My "audio bus" is a 14MHz WDC 6502 and a 10ns SRAM, which are separated from the 3.5MHz main bus by a 74CBT16210 20-bit bus switch. The 14MHz PHI2 is tied to BE as well as the !OE of the bus switch, so the idea was that on PHI2/BE High it would separate the busses and let Audio CPU take control. Then on PHI2/BE Low it would join the busses while the Audio CPU was high-impedance.
Of course, this just makes the main CPU not run right when this audio bus is connected at all. It crashes immediately if I untie the bus switch !OE from Vcc.
