Re: 16-bit/32-bit 65C816 random number generator
Posted: Mon Oct 13, 2025 8:45 pm
gfoot wrote:
BigDumbDinosaur wrote:
Since I have a free-running, 16-bit hardware timer counting down from $FFFF to $0000 at the rate of ~57,000 times per second, it seems I could read the timer, write it to state+0, read the timer with a check that it has changed since the previous read, write to state+2, and repeat until state+6 is initialized. I think a little more entropy could be introduced by inserting a WAI instruction between successive timer reads.
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So the sequence of random numbers you'd get would depend only on the counter's value at time of RNG initialisation, and depending what your system does before this point, that counter value could be rather consistent.
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On the other hand, if something like reading data from the serial port or disk is involved, those operations will add some variance to the time it takes your system to reach this point and hence the counter value, and that's good, the more of that sort of thing the better!
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It would be even better if you had a faster counter available, e.g. T1 on a 6522 which counts down at the rate of the system clock. The low bits of this will be more sensitive to minor changes in elapsed time, amplifying any variance to span a wider range of seed values.
I’m currently running the timer at the rate of X1 ÷ 16, where X1 is the DUART’s clock frequency (3.6864 MHz). That produces an effective timer frequency of 115.2 KHz, due to the timer changing phase on every other transition of the X1 clock, i.e., one-half the X1 rate. That rate produces an interval of 8.68 µsecs between timer “ticks,” which is pretty coarse. With the timer running at that rate, the 65C816 (which runs at 16 MHz in POC V1.3) could do many consecutive reads of the timer before it changes, despite the one-cycle wait-state that occurs on DUART accesses.
The timer may also be configured to run at X1 ÷ 1, which would reduce the interval to 0.54 µsecs. Even at that rate, closely-spaced reads of the timer are likely to return the same value.
Beyond that, the 28L92 has a provision for driving the timer with an external clock signal of 8 MHz maximum, which would produce an effective timer frequency of 4 MHz, an interval of 0.25 µsecs. That would all but eliminate the likelihood of consecutive reads returning the same value. However, using an external clock would mean adding a third oscillator to the unit, or using a flop to tap off a signal from the Ø2 clock.
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WAI itself is not inherently a source of entropy unless you have other hardware interrupts that fire at different moments each time you boot your system.
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Whatever entropy you're able to find, if the range of likely values spans less than 16 bits I think it would be best to manipulate it a bit before writing it into the state, to ensure that the variant bits are having effects across the whole of the word.
BigEd wrote:
I think it might be better to XOR any extra source bytes, rather than to STO them, to mix in the new with the existing. Or ADC might be similar in effect.
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I do believe latency of spinning disks is a good source of entropy - it's affected by turbulence in the air layer.
However, in my POC units, despite running the host adapter in SCSI-1 asynchronous mode (the slowest mode), the bus is still substantially faster than the POC unit.