6502.org

The 6502 Microprocessor Resource
http://forum.6502.org/

Assistance with 65C816 to FPGA UART Communication Issue

http://forum.6502.org/viewtopic.php?t=7925

Page 2 of 3

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Fri Jan 12, 2024 10:56 pm
by hoglet
Jmstein7 wrote:
Curious to know what your thoughts are.
Something is stopping the ACIA from sending.

Where does CTSB come from?

It looks like it's driven from this m_rtsn in module:
https://github.com/jmstein7/65C816_to_F ... inx_UART.v

But there is nothing actually driving m_rtsn.

Dave

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Fri Jan 12, 2024 11:20 pm
by Jmstein7
hoglet wrote:
Something is stopping the ACIA from sending.

Where does CTSB come from?

It looks like it's driven from this m_rtsn in module:
https://github.com/jmstein7/65C816_to_F ... inx_UART.v

But there is nothing actually driving m_rtsn.

Dave
RTS and CTS are "short circuited" as if they were physically jumpered together:

Code: Select all

Xilinx_UART UART_A(
  .m_rxd(uart_rx), // Serial Input (required)
  .m_txd(uart_tx), // Serial Output (required)
  .m_rtsn(cts), // Request to Send out(optional)
  .m_ctsn(rts), // Clear to Send in(optional)
//  additional ports here
  .acia_tx(tx),
  .acia_rx(rx)

);
tx is the signal out of LIV2's ACIA:

Code: Select all

ACIA acia_a(
    .RESET(resb),
    .PHI2(phi2),
    .phi_enable(phi_enable),
    .CS(acia_e),
    .RWN(rwb),
    .RS(reg_select),
    .DATAIN(acia_in),
    .DATAOUT(acia_out),
    .XTLI(acia_clk),
    .RTSB(rts),
    .CTSB(cts),
    .DTRB(),
    .RXD(rx),
    .TXD(tx),
    .IRQn(1'b1)
   );
If something is stopping it, it must be somewhere here:
https://github.com/jmstein7/65c816_to_X ... /6551-ACIA

I'm going through the VDHL here like a madman, but I can't seem to find the block. Also, VHDL really isn't my strong suit.

Jonathan

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Fri Jan 12, 2024 11:48 pm
by hoglet
Jmstein7 wrote:
RTS and CTS are "short circuited" as if they were physically jumpered together:

Code: Select all

Xilinx_UART UART_A(
  .m_rxd(uart_rx), // Serial Input (required)
  .m_txd(uart_tx), // Serial Output (required)
  .m_rtsn(cts), // Request to Send out(optional)
  .m_ctsn(rts), // Clear to Send in(optional)
//  additional ports here
  .acia_tx(tx),
  .acia_rx(rx)

);
I don't think they are...

If you look inside Xilinx_UART.v, nothing is driving the m_rtsn output:
https://github.com/jmstein7/65C816_to_F ... inx_UART.v

If the intent is that module loops cts back to rts, then you need to add:

Code: Select all

assign m_rtsn = m_ctsn;
If you look carefully in the Vivado logs, there will be a warning to the effect that m_rtsn is undriven.

Dave

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Sat Jan 13, 2024 12:17 am
by Jmstein7
hoglet wrote:

If you look inside Xilinx_UART.v, nothing is driving the m_rtsn output:
https://github.com/jmstein7/65C816_to_F ... inx_UART.v

If the intent is that module loops cts back to rts, then you need to add:

Code: Select all

assign m_rtsn = m_ctsn;
If you look carefully in the Vivado logs, there will be a warning to the effect that m_rtsn is undriven.

Dave
Just tried it:

Code: Select all

//  user logic here
assign m_txd = acia_tx;
assign acia_rx = m_rxd;

assign m_rtsn = m_ctsn;
It didn't make a difference. Must be something else. J

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Sat Jan 13, 2024 8:39 am
by hoglet
Jmstein7 wrote:
It didn't make a difference. Must be something else.
Fair enough, but I think it was needed if you want to loop back the flow control signals.

A couple more things might be useful:
- Can you post a copy of the warnings from Vivado?
- Can you post the assembler source for your monitor ROM?

Maybe I'm barking up the wrong tree, but I think it could still be a flow control issue.

The ACIA needs its CTSB input low in order to send. You are currently driving this from the ACIA's RTSB output (looped back though the Xilinx_UART module).

Can you add cts to the set of signals you monitor externally? You should see this go high on reset, then go low when your monitor initialized the UART.

What value is your monitor writing to the UART command register?

Dave

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Sat Jan 13, 2024 2:42 pm
by Jmstein7
hoglet wrote:
Fair enough, but I think it was needed if you want to loop back the flow control signals.

A couple more things might be useful:
- Can you post a copy of the warnings from Vivado?
- Can you post the assembler source for your monitor ROM?

Maybe I'm barking up the wrong tree, but I think it could still be a flow control issue.

The ACIA needs its CTSB input low in order to send. You are currently driving this from the ACIA's RTSB output (looped back though the Xilinx_UART module).

Can you add cts to the set of signals you monitor externally? You should see this go high on reset, then go low when your monitor initialized the UART.

What value is your monitor writing to the UART command register?

Dave
I think this will help.
This is the little jump at the beginning:

Code: Select all

C35D   A9 10                LDA #$10
C35F   8D 03 80             STA $8003
C362   A9 C9                LDA #$C9
C364   8D 02 80             STA $8002
C367   60                   RTS
C368   18                   CLC
C369   AD 01 80             LDA $8001
C36C   29 08                AND #$08
C36E   F0 04                BEQ LC374
C370   AD 00 80             LDA $8000
C373   38                   SEC
C374   60         LC374     RTS
C375   48                   PHA
C376   AD 01 80   LC376     LDA $8001
C379   29 10                AND #$10
C37B   F0 F9                BEQ LC376
C37D   68                   PLA
C37E   8D 00 80             STA $8000
C381   20 00 EF             JSR $EF00
C384   60                   RTS
And this is a disassembly from the point where the reset vector starts the execution, $C385:

Code: Select all

* = $C385
C385   D8         LC385     CLD
C386   58                   CLI
C387   20 5D C3             JSR $C35D
C38A   A9 0D                LDA #$0D
C38C   20 CF C4             JSR LC4CF
C38F   A9 0F                LDA #$0F
C391   85 EC                STA $EC
C393   A9 EF                LDA #$EF
C395   85 ED                STA $ED
C397   20 E1 C4             JSR LC4E1
C39A   A9 0D                LDA #$0D
C39C   20 CF C4             JSR LC4CF
C39F   A9 83                LDA #$83
C3A1   85 EC                STA $EC
C3A3   A9 EF                LDA #$EF
C3A5   85 ED                STA $ED
C3A7   20 E1 C4             JSR LC4E1
C3AA   A9 0D                LDA #$0D
C3AC   20 CF C4             JSR LC4CF
C3AF   A9 BF                LDA #$BF
C3B1   85 EC                STA $EC
C3B3   A9 EF                LDA #$EF
C3B5   85 ED                STA $ED
C3B7   20 E1 C4             JSR LC4E1
C3BA   A9 0D                LDA #$0D
C3BC   20 CF C4             JSR LC4CF
C3BF   A9 9B      LC3BF     LDA #$9B
C3C1   C9 88      LC3C1     CMP #$88
C3C3   F0 13                BEQ LC3D8
C3C5   C9 9B                CMP #$9B
C3C7   F0 03                BEQ LC3CC
C3C9   C8                   INY
C3CA   10 19                BPL LC3E5
C3CC   A9 DC      LC3CC     LDA #$DC
C3CE   20 CF C4             JSR LC4CF
C3D1   A9 8D      LC3D1     LDA #$8D
C3D3   20 CF C4             JSR LC4CF
C3D6   A0 01                LDY #$01
C3D8   88         LC3D8     DEY
C3D9   30 F6                BMI LC3D1
C3DB   A9 A0                LDA #$A0
C3DD   20 CF C4             JSR LC4CF
C3E0   A9 88                LDA #$88
C3E2   20 CF C4             JSR LC4CF
C3E5   AD 01 80   LC3E5     LDA $8001
C3E8   29 08                AND #$08
C3EA   F0 F9                BEQ LC3E5
C3EC   AD 00 80             LDA $8000
C3EF   C9 60                CMP #$60
C3F1   30 02                BMI LC3F5
C3F3   29 5F                AND #$5F
C3F5   09 80      LC3F5     ORA #$80
C3F7   99 00 02             STA $0200,Y
C3FA   20 CF C4             JSR LC4CF
C3FD   C9 8D                CMP #$8D
C3FF   D0 C0                BNE LC3C1
C401   A0 FF                LDY #$FF
C403   A9 00                LDA #$00
C405   AA                   TAX
C406   0A         LC406     ASL A
C407   85 EB      LC407     STA $EB
C409   C8         LC409     INY
C40A   B9 00 02   LC40A     LDA $0200,Y
C40D   C9 8D                CMP #$8D
C40F   F0 C0                BEQ LC3D1
C411   C9 AE                CMP #$AE
C413   90 F4                BCC LC409
C415   F0 F0                BEQ LC407
C417   C9 BA                CMP #$BA
C419   F0 EB                BEQ LC406
C41B   C9 D2                CMP #$D2
C41D   F0 3B                BEQ LC45A
C41F   C9 CC                CMP #$CC
C421   D0 03                BNE LC426
C423   4C EE C4             JMP LC4EE
C426   C9 D8      LC426     CMP #$D8
C428   D0 03                BNE LC42D
C42A   4C 00 C2             JMP $C200
C42D   86 E8      LC42D     STX $E8
C42F   86 E9                STX $E9
C431   84 EA                STY $EA
C433   B9 00 02   LC433     LDA $0200,Y
C436   49 B0                EOR #$B0
C438   C9 0A                CMP #$0A
C43A   90 06                BCC LC442
C43C   69 88                ADC #$88
C43E   C9 FA                CMP #$FA
C440   90 11                BCC LC453
C442   0A         LC442     ASL A
C443   0A                   ASL A
C444   0A                   ASL A
C445   0A                   ASL A
C446   A2 04                LDX #$04
C448   0A         LC448     ASL A
C449   26 E8                ROL $E8
C44B   26 E9                ROL $E9
C44D   CA                   DEX
C44E   D0 F8                BNE LC448
C450   C8                   INY
C451   D0 E0                BNE LC433
C453   C4 EA      LC453     CPY $EA
C455   D0 0F                BNE LC466
C457   4C CC C3             JMP LC3CC
C45A   20 60 C4   LC45A     JSR LC460
C45D   4C BF C3             JMP LC3BF
C460   6C E4 00   LC460     JMP ($00E4)
C463   4C BF C3             JMP LC3BF
C466   24 EB      LC466     BIT $EB
C468   50 0D                BVC LC477
C46A   A5 E8                LDA $E8
C46C   81 E6                STA ($E6,X)
C46E   E6 E6                INC $E6
C470   D0 98                BNE LC40A
C472   E6 E7                INC $E7
C474   4C 0A C4   LC474     JMP LC40A
C477   30 2B      LC477     BMI LC4A4
C479   A2 02                LDX #$02
C47B   B5 E7      LC47B     LDA $E7,X
C47D   95 E5                STA $E5,X
C47F   95 E3                STA $E3,X
C481   CA                   DEX
C482   D0 F7                BNE LC47B
C484   D0 14      LC484     BNE LC49A
C486   A9 8D                LDA #$8D
C488   20 CF C4             JSR LC4CF
C48B   A5 E5                LDA $E5
C48D   20 BC C4             JSR LC4BC
C490   A5 E4                LDA $E4
C492   20 BC C4             JSR LC4BC
C495   A9 BA                LDA #$BA
C497   20 CF C4             JSR LC4CF
C49A   A9 A0      LC49A     LDA #$A0
C49C   20 CF C4             JSR LC4CF
C49F   A1 E4                LDA ($E4,X)
C4A1   20 BC C4             JSR LC4BC
C4A4   86 EB      LC4A4     STX $EB
C4A6   A5 E4                LDA $E4
C4A8   C5 E8                CMP $E8
C4AA   A5 E5                LDA $E5
C4AC   E5 E9                SBC $E9
C4AE   B0 C4                BCS LC474
C4B0   E6 E4                INC $E4
C4B2   D0 02                BNE LC4B6
C4B4   E6 E5                INC $E5
C4B6   A5 E4      LC4B6     LDA $E4
C4B8   29 0F                AND #$0F
C4BA   10 C8                BPL LC484
C4BC   48         LC4BC     PHA
C4BD   4A                   LSR A
C4BE   4A                   LSR A
C4BF   4A                   LSR A
C4C0   4A                   LSR A
C4C1   20 C5 C4             JSR LC4C5
C4C4   68                   PLA
C4C5   29 0F      LC4C5     AND #$0F
C4C7   09 B0                ORA #$B0
C4C9   C9 BA                CMP #$BA
C4CB   90 02                BCC LC4CF
C4CD   69 06                ADC #$06
C4CF   48         LC4CF     PHA
C4D0   29 7F                AND #$7F
C4D2   8D 00 80             STA $8000
C4D5   20 00 EF             JSR $EF00
C4D8   AD 01 80   LC4D8     LDA $8001
C4DB   29 10                AND #$10
C4DD   F0 F9                BEQ LC4D8
C4DF   68                   PLA
C4E0   60                   RTS
C4E1   A0 00      LC4E1     LDY #$00
C4E3   B1 EC      LC4E3     LDA ($EC),Y
C4E5   F0 06                BEQ LC4ED
C4E7   20 CF C4             JSR LC4CF
C4EA   C8                   INY
C4EB   D0 F6                BNE LC4E3
C4ED   60         LC4ED     RTS
C4EE   D8         LC4EE     CLD
C4EF   18                   CLC
C4F0   A2 00                LDX #$00
C4F2   9A                   TXS
C4F3   A9 00                LDA #$00
C4F5   85 AA                STA $AA
C4F7   A9 01                LDA #$01
C4F9   85 AB                STA $AB
C4FB   A9 00                LDA #$00
C4FD   A8                   TAY
C4FE   91 AA      LC4FE     STA ($AA),Y
C500   C8                   INY
C501   CA                   DEX
C502   D0 FA                BNE LC4FE
C504   A9 00                LDA #$00
C506   85 AA                STA $AA
C508   A9 00                LDA #$00
C50A   85 AB                STA $AB
C50C   A9 00                LDA #$00
C50E   A8                   TAY
C50F   91 AA      LC50F     STA ($AA),Y
C511   C8                   INY
C512   CA                   DEX
C513   D0 FA                BNE LC50F
C515   A9 0D                LDA #$0D
C517   20 CF C4             JSR LC4CF
C51A   A9 A2                LDA #$A2
C51C   85 EC                STA $EC
C51E   A9 EF                LDA #$EF
C520   85 ED                STA $ED
C522   20 E1 C4             JSR LC4E1
C525   A9 0D                LDA #$0D
C527   4C 85 C3             JMP LC385
C52A   78                   SEI
C52B   48                   PHA
C52C   DA                   ???                ;%11011010
C52D   5A                   ???                ;%01011010 'Z'
C52E   A9 01                LDA #$01
C530   85 F2                STA $F2
C532   E6 F3                INC $F3
C534   7A                   ???                ;%01111010 'z'
C535   FA                   ???                ;%11111010
C536   68                   PLA
C537   58                   CLI
C538   40                   RTI
C539   78                   SEI
C53A   48                   PHA
C53B   DA                   ???                ;%11011010
C53C   5A                   ???                ;%01011010 'Z'
C53D   7A                   ???                ;%01111010 'z'
C53E   FA                   ???                ;%11111010
C53F   68                   PLA
C540   58                   CLI
C541   40                   RTI
C542   45 39                EOR $39
C544   AA                   TAX
C545   A5 38                LDA $38
C547   5D 00 EE             EOR $EE00,X
C54A   85 39                STA $39
C54C   BD 00 ED             LDA $ED00,X
C54F   85 38                STA $38
C551   60                   RTS
Jonathan

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Sat Jan 13, 2024 3:42 pm
by hoglet

Code: Select all

C362   A9 C9                LDA #$C9 ; 1100 1001
C364   8D 02 80             STA $8002
Bits 3..2 (=10) should configure the ACIA to set RTSB low, which is what you need if you are looping this back to CTSB. But it would be good to confirm that by exposing the rts and cts nets and scoping then.

Dave

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Sat Jan 13, 2024 3:53 pm
by Jmstein7
hoglet wrote:

Code: Select all

C362   A9 C9                LDA #$C9 ; 1100 1001
C364   8D 02 80             STA $8002
Bits 3..2 (=10) should configure the ACIA to set RTSB low, which is what you need if you are looping this back to CTSB. But it would be good to confirm that by exposing the rts and cts nets and scoping then.

Dave
Doing some runs right now 8)

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Sat Jan 13, 2024 5:34 pm
by Jmstein7
hoglet wrote:

Code: Select all

C362   A9 C9                LDA #$C9 ; 1100 1001
C364   8D 02 80             STA $8002
Bits 3..2 (=10) should configure the ACIA to set RTSB low, which is what you need if you are looping this back to CTSB. But it would be good to confirm that by exposing the rts and cts nets and scoping then.

Dave
And now, nothing is working?

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Sat Jan 13, 2024 7:28 pm
by SamCoVT
This looks like the CPU is stuck running the same instruction(s) over and over. I think we're back to needing to verify that your base hardware works piece by piece. Have you done this combo of CPU + level shifters + FPGA before?

I still recommend making a new assembly file that has only the reset vector and instructions to initialize the ACIA and send a character without any RAM usage at all (eg no JSRs, but JMP is OK). If you do not know how to do this, let us know and we can help you - it's hard to gauge what kind of assistance you may need.

There are many reasons your circuit could be misbehaving (or even partially working and partially misbehaving), so writing a short program that does not need RAM (using only registers and writing only to the ACIA) helps us by eliminating some of the possibilities from even being able to happen. Note that your emulated RAM needs your level shifters to work properly in both directions (on the data bus), while your emulated ROM only needs the level shifters to work in one direction (albeit address and data are in different directions).

I think there is an issue in your ACIA (which might be the handshaking line not being driven and you may already be on the way to fixing that), but I think your base hardware may have other issues as well. We need the base hardware working before we can fully diagnose the ACIA, but Dave's (hoglet's) suggestion of posting your Vivado warnings is very good advice and may point to whatever issue your ACIA has.

A schematic showing the CPU and everything hooked up to it would be a good start, along with a photo of the back side of your board. Did you receive your oscilloscope and do you know how to use it? Some quick scope shots on both sides of your level shifters would quickly show us if you have signal integrity issues - one address line (ideally a lower bit that is changing often like A0) , one data bit, and one control line is probably enough to get started. Those can certainly cause the "works sometimes" kinds of issues. You might also check your power rails and make sure they are "reasonably" steady.

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Sat Jan 13, 2024 8:12 pm
by Jmstein7
SamCoVT wrote:
Did you receive your oscilloscope and do you know how to use it? Some quick scope shots on both sides of your level shifters would quickly show us if you have signal integrity issues - one address line (ideally a lower bit that is changing often like A0) , one data bit, and one control line is probably enough to get started. Those can certainly cause the "works sometimes" kinds of issues. You might also check your power rails and make sure they are "reasonably" steady.
Yes, just got it. I'll put it together and take some measurements for upload.

Jonathan

edit: As soon as I can figure out how to operate it :oops:

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Sun Jan 14, 2024 1:22 am
by SamCoVT
Step 1 is to calibrate your probes. The manual will likely have the details, but the basic procedure is:
Hook a probe to CH1
If probe has a 1X/10X switch, change it to 10X
Connect probe to probe compensator built into scope (this is just a square wave generator). There is usually a metal terminal for the probe's hook tip and another terminal right next to it for the ground alligator clip.
Press the AUTOSET button - you should see a square wave. We do not care about the frequency or size of this waveform - only it's shape.
There is a little screw adjustment either on the probe body or on the BNC connector where it plugs into the scope. Adjust this (there is usually a little plastic screwdriver type thing for doing this) until the signal rises crisply with no overshoot (I normally adjust until there is overshoot and then dial it back until it is perfectly flat on top). Your probe is now compensated for use with this scope. You usually only need to redo this if you move the probes to a different scope or you are about to look at signals where the high frequency ringing at the edges of signals really matters to you (and it DOES for us here).
Repeat with any other probes you have until they are calibrated.

Here's the "I just need to see something on my screen" method that often (but not always) works:
Plug probe into CH1 and set it to 10X if it has a 1X/10X switch.
Connect hook tip to signal and ground clip to ground (we can talk about why the alligator ground isn't great for high speed signals later) [Edit - I originally forgot this step!]
Press the AUTOSET button. This will only work if there are CHANGES on the signal, so plugging into something like A0 that will be constantly changing is a good idea. If you plug into something like your 3.3V power rail and press AUTOSET, it will just zoom into the fuzzy wiggles at 10mV/division because that was the repetitive signal that it found.

For actual use, you will probably want to learn how to set up triggering.
If you let us know the model# of your equipment, we can provide more detailed suggestions (and will also know the capabilities of your equipment).

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Sun Jan 14, 2024 2:20 am
by Jmstein7
SamCoVT wrote:
Step 1 is to calibrate your probes. The manual will likely have the details, but the basic procedure is:
Hook a probe to CH1
If probe has a 1X/10X switch, change it to 10X
Connect probe to probe compensator built into scope (this is just a square wave generator). There is usually a metal terminal for the probe's hook tip and another terminal right next to it for the ground alligator clip.
Press the AUTOSET button - you should see a square wave. We do not care about the frequency or size of this waveform - only it's shape.
There is a little screw adjustment either on the probe body or on the BNC connector where it plugs into the scope. Adjust this (there is usually a little plastic screwdriver type thing for doing this) until the signal rises crisply with no overshoot (I normally adjust until there is overshoot and then dial it back until it is perfectly flat on top). Your probe is now compensated for use with this scope. You usually only need to redo this if you move the probes to a different scope or you are about to look at signals where the high frequency ringing at the edges of signals really matters to you (and it DOES for us here).
Repeat with any other probes you have until they are calibrated.

Here's the "I just need to see something on my screen" method that often (but not always) works:
Plug probe into CH1 and set it to 10X if it has a 1X/10X switch.
Connect hook tip to signal and ground clip to ground (we can talk about why the alligator ground isn't great for high speed signals later) [Edit - I originally forgot this step!]
Press the AUTOSET button. This will only work if there are CHANGES on the signal, so plugging into something like A0 that will be constantly changing is a good idea. If you plug into something like your 3.3V power rail and press AUTOSET, it will just zoom into the fuzzy wiggles at 10mV/division because that was the repetitive signal that it found.

For actual use, you will probably want to learn how to set up triggering.
If you let us know the model# of your equipment, we can provide more detailed suggestions (and will also know the capabilities of your equipment).
That worked! Got it going. Now - what am I looking for here? Any specific tests you'd like to see? I've never used an oscilloscope before for anything. But, looking at the data sheet for the level shifters (TX0108E), and, of course, the data on pages 25 through 28 of the 65C816 datasheet, I can see why this might not be as simple as a little verilog. No matter - I'm determined to make this work.

Jonathan

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Sun Jan 14, 2024 3:45 am
by SamCoVT
I think something like A0 and D0 on each side of your level shifters would be a good place to start because they change a lot. You can press the RUN/STOP button to pause the action. I press it multiple times until I see what I'm looking for (in this case, we'd like a high to low transition and low to high transition on the screen. What you will soon see is that your signals don't look as nice and pretty as your logic analyzer would tell you, but the logic analyzer helps by hiding all of that when it's not important to let you focus on the logic. If your scope has a USB port on the front, you can usually export screenshots. Otherwise, a photo of the screen works fine.

Also, check your messages (on the forum).

Re: Assistance with 65C816 to FPGA UART Communication Issue

Posted: Sun Jan 14, 2024 8:13 am
by hoglet
Jmstein7 wrote:
I just happen to have ordered a new oscilloscope that's arriving today.
Which make/model did you buy?
All times are UTC
Page 2 of 3

Powered by phpBB® Forum Software © phpBB Limited