CMOS compatible SRAM

[Dr Jefyll]

GlennSmith wrote:

... and from the same document, this little snippet :

Thanks for your post.

IMO, TI could have been more explicit with what they're saying. Let's be clear that they're talking about a situation where two different supply voltages are involved.

FWIW, let's look at the situation where there are NOT two different supply voltages involved (ie, if both devices are powered by the same voltage).

At the risk of stating the obvious, the pullup will hardly make any difference, because the totem-pole output will pull to the rail anyway. Although the pullup does appear in parallel with the upper FET, the FET's On Resistance is likely to be far lower than the resistance of the pullup, making the latter pointless.

-- Jeff

[GlennSmith]

... unless they are maybe implying that internally their TTL compatible CMOS is actually internally powered through an LDO as was surmised above.
NYWAY, I'm reassured that it has a reasonable chance to work, so I'm moving-on to other potential gotchas in my design. Thanks all.

[Chromatix]

One sensible way of converting a TTL signal to a CMOS one is to insert a jellybean buffer, either of the 74AHCT family (which has TTL compatible inputs and CMOS outputs) or a 74AHC family Schmitt trigger (for which the inputs will be TTL compatible). The 74HCT and 74HC families can also be used if you don't need the speed of the AHC logic.

On a bidirectional bus you'll need to be careful to use tristate buffers, and switch off the outputs whenever a conflicting drive may be present.

Also note that Vih and Voh of CMOS-3.3V logic is pretty close to TTL and will likely be compatible. That might be a good reason in itself to go for a 3.3V design.