6502.org

Posted: **Wed May 14, 2025 7:17 pm**

plasmo wrote:

We’ve just had a recent conversation in the programmable logic device section about mapping 1 meg memory into 64 16K pages using ATF1502. 16K page size is do-able, but the logic and register files increase rapidly as page size decrease to 8K or 4K. I don’t think ATF15xx CPLD is large enough to map 1 meg memory into 256 4K pages.
Bill
Edit, If the page size is increased to 32K, then the mapping becomes almost trivial. I have a small Z80 SBC that has 32 meg memory on board. I’ve mapped 8 meg to 256 32K banks in CPLD and was thinking about mapping 32 meg memory to 1024 banks, but gave up, not because the logic is hard, it isn’t, but because I don’t want to explain why 1024 32K banks is ever useful on a 14Mhz Z80!

Im looking at "128 or 256" macrocells, the ATF15xx (the 08?) in that series, you 'the Genius Dinosaur' and a few other around here have done, the 6502 RISC on cpld etc, I am thinking if I use the Port, and a 4bit control unit, I might be ok on 128, 256 MC is okay too. give or take, I dont want a big fpga or anything, though they are so cheap now... If I can use a simple PIC16, I might do that too, though I think its pushing it and Id like better integration.

Dr Jefyll wrote:

wayfarer wrote:

I will be certain to look over your design, that is very much a basic part of what we are trying to accomplish

Although I successfully reproduced 6509 behavior, I have mixed feelings about that behavior.
What's wonderful (and highly unusual!) about the 6509 scheme is that it looks at the extra memory space in terms of entire, 64K blocks (not just an awkward series of "windows" of 16K or whatever). Obviously the 6509 is no '816, but the 6509 designers did have the excellent good sense to treat the memory space as the '816 does (ie, blocks which are a full 64K each).

Unfortunately, the 6509 also has a few warts, probably because the designers were short of time or other resources. In order to preserve compatibility I didn't attempt any changes to moderate those shortcomings. But if you have any serious interest in a 6509-like approach then let me know, as I have some suggestions in that regard.
-- Jeff

I want full 20b address space on the ISAC, which will be the permanent bus master according to dma, though Im thinking it might make use of the SYNC pin to act more like a co-processor. Any suggestions here are welcome, Im trying to extend the 6502, by integrating a space mcu to the 6522 (actually just a single port interface adapter.. 652'something), and maybe keeping a few timers or interrupt queues, not much really. In this case, as its a 4b control processor with an 8b data bus and 20b address bus, control lines etc, or I have to add an mcu, or extra 6502 to the board. what were you thinking?

fachat wrote:

The 6509 is an interesting approach. I like it because it is symmetrical, no bank is extra except 15 where it boots.
However, being able to cross access banks only with indirect y indexed accesses is not very handy.
The Commodore 500/600/700 BASIC of those machines that used it is quite a bit slower
André

this would be more of a bus controller and the cpu, would require 'segment/bank/slot' access from ISAC, and operates as anything else does, or any 6502 using devices with i/o outside of the normal 64k space. Only a 6502 with a bigger data bus will do this on one command, without using a prefetch decoder to do so, this can maybe act in a fashion to do so.

here is what I have so far:

Code: Select all

00-01:  WX
YZ-03:  Data 7 downto 0
     04:  AEN, ALE, T/C, RES
     05:  DREQ/DACK
     06:  IRQS, MEM R//W
     07:  IO, RDY, Clk, R/W
08-BC:  Address 19 downto 0
     DE: Control, Arithmetic Flags
       F:  Stack

in terms of assigning my 16 registers from my 6404 mcu, im trying to put on here. I would almost drop the ALU, though thats its own problem. Im short 1-2 lines for ISA, and I think i get one from SYNC and one from IRQ in. maybe. I have the X bit still

so here the goal is to get the 6502, on the 8b ISA bus, some things, like R/W, can use an inverter, or inverting line-driver, and be split out to 2 lines, things like this can convert the 6800 style, to the 8080 bus. This should, let ISA cards use this bus, and the 6502 to talk to them.

Posted: **Fri May 16, 2025 1:21 am**

new book!
its like a deeper exploration of the specification with some clarity.
might come in handy here

6502.org

ISAC --a chip for the 6502 on ISA

Re: ISAC --a chip for the 6502 on ISA

Re: ISAC --a chip for the 6502 on ISA